| 2003 | FPGA | An FPGA architecture with built-in error correction capability. | Parag K. Lala, B. Kiran Kumar |
| 2003 | IOLTS | Fault Injection in Digital Logic Circuits at the VHDL Level. | S. R. Seward, Parag K. Lala |
| 2003 | IOLTS | On-Line Error Detecting Constant Delay Adder. | Whitney J. Townsend, Jacob A. Abraham, Parag K. Lala |
| 2003 | ITC | On-line Detection of Faults in Carry-Select Adders. | B. Kiran Kumar, Parag K. Lala |
| 2003 | ITC | Fault Injection for Verifying Testability at the VHDL Level. | S. R. Seward, Parag K. Lala |
| 2002 | IOLTS | An Architecture for Self-Healing Digital Systems. | Parag K. Lala, B. Kiran Kumar |
| 2001 | IOLTS | An Approach for Designing On-Line Testable State Machines. | Parag K. Lala, Mark G. Karpovsky |
| 1999 | FPGA | Self-Checking Logic Design for LUT-Based FPGAs. | Parag K. Lala, Alfred L. Burress |
| 1999 | ISCAS | A technique for designing self-checking logic for FPGAs. | Parag K. Lala, Alfred L. Burress |
| 1997 | ITC | On-Line Testable Logic Desgin for FPGA Implementation. | Alfred L. Burress, Parag K. Lala |
| 1993 | VTS | Input and output encoding techniques for on-line error detection in combinational logic circuits. | Fadi Y. Busaba, Parag K. Lala |
| 1992 | VTS | A new technique for totally self-checking CMOS circuit design for stuck-on and stuck-off faults. | Manjit S. Cheema, Parag K. Lala |
| 1992 | VTS | A concurrent checking scheme for single and multibit errors in logic circuits. | B. Kolla, Parag K. Lala, K. C. Yarlagadda |
| 1991 | VTS | An approach for designing self-checking logic using residue codes. | Parag K. Lala, Fadi Y. Busaba, K. C. Yarlagadda |
| 1986 | ITC | On Built-In Testing of VLSI Chips. | Parag K. Lala |
| 1986 | ITC | A Concurrent Testing Strategy for PLAs. | Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala |