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Praveen Raghavan

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

34

Venues

14

Active years

2006–2017

Best venue rank

A*

Where they publish

Papers

34 indexed papers, newest first.

YearVenueTitleAuthors
2017DACVertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes.Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang
2017DATEWave pipelining for majority-based beyond-CMOS technologies.Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amar, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins
2017ICCADIR-drop aware Design & technology co-optimization for N5 node with different device and cell height options.Luca Mattii, Dragomir Milojevic, Peter Debacker, Yasser Sherazi, Mladen Berekovic, Praveen Raghavan
2017ICCDPatterning Aware Design Optimization of Selective Etching in N5 and Beyond.Yibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-Han Kim, Praveen Raghavan, David Z. Pan
2017ICCDUltra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching.Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi
2016DDECSComparative BTI analysis for various sense amplifier designs.Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Praveen Raghavan, Francky Catthoor
2016ICCADHow much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?Bon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan, Sung Kyu Lim
2016ISCASPower noise in 14, 10, and 7 nm FinFET CMOS technologies.Ravi Patel, Eby G. Friedman, Praveen Raghavan
2016ISLPEDPhysical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs.Bon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan, Diederik Verkest, Aaron Thean, Sung Kyu Lim
2015DATEImpact of interconnect multiple-patterning variability on SRAMs.Ioannis Karageorgos, Michele Stucchi, Praveen Raghavan, Julien Ryckaert, Zsolt Tokei, Diederik Verkest, Rogier Baert, Sushil Sakhare, Wim Dehaene
2015VTSIntegral impact of BTI and voltage temperature variation on SRAM sense amplifier.Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Halil Kukner, Pieter Weckx, Praveen Raghavan, Francky Catthoor
2014DATEResolving the memory bottleneck for single supply near-threshold computing.Tobias Gemmeke, Mohamed M. Sabry, Jan Stuijt, Praveen Raghavan, Francky Catthoor, David Atienza
2014DATEBias Temperature Instability analysis of FinFET based SRAM cells.Seyab Khan, Innocent Agbo, Said Hamdioui, Halil Kukner, Ben Kaczer, Praveen Raghavan, Francky Catthoor
2014DATEFeasibility exploration of NVM based I-cache through MSHR enhancements.Manu Komalan, Jos Ignacio Gmez Prez, Christian Tenllado, Praveen Raghavan, Matthias Hartmann, Francky Catthoor
2014DSDNBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes.Halil Kukner, Pieter Weckx, Sebastien Morrison, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, Guido Groeseneken
2014DSDMajority Logic Synthesis for Spin Wave Technology.Odysseas Zografos, Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Praveen Raghavan, Giovanni De Micheli
2014VLSIDHard versus Soft Software Defined Radio.Wim Meeus, Tom Vander Aa, Praveen Raghavan, Dirk Stroobandt
2013DACEarly exploration for platform architecture instantiation with multi-mode application partitioning.Prashant Agrawal, Praveen Raghavan, Matthias Hartmann, Namita Sharma, Liesbet Van der Perre, Francky Catthoor
2013DSDMemristor-Based (ReRAM) Data Memory Architecture in ASIP Design.Matthias Hartmann, Praveen Raghavan, Liesbet Van der Perre, Prashant Agrawal, Wim Dehaene
2013ETSBias temperature instability analysis in SRAM decoder.Seyab Khan, Said Hamdioui, Halil Kukner, Praveen Raghavan, Francky Catthoor
2013ICASSPData memory optimization in LTE downlink.Namita Sharma, Tom Vander Aa, Prashant Agrawal, Praveen Raghavan, Preeti Ranjan Panda, Francky Catthoor
2012DDECSBTI impact on logical gates in nano-scale CMOS technology.Seyab Khan, Said Hamdioui, Halil Kukner, Praveen Raghavan, Francky Catthoor
2012DSDPartitioning and Assignment Exploration for Multiple Modes of IEEE 802.11n Modem on Heterogeneous MPSoC Platforms.Prashant Agrawal, Kanishk Sugand, Martin Palkovic, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor
2012DSDImpact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model.Halil Kukner, Pieter Weckx, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, Guido Groeseneken
2012VTCAlgorithm-Architecture Co-Optimization of Area-Efficient SDR Baseband for Highly Diversified Digital TV Standards.Kiyotaka Kobayashi, Hidekuni Yomo, Min Li, Raf Appeltans, Hans Cappelle, Amir Amin, Assa Couvreur, Matthias Hartmann, Andr Bourdoux, Praveen Raghavan, Antoine Dejonghe, Liesbet Van der Perre
2011DSDAn Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating.Ittetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui, Praveen Raghavan, Francky Catthoor
2011ICASSPDart - a high level software-defined radio platform model for developing the run-time controller.Martin Palkovic, Jeroen Declerck, Praveen Raghavan, Antoine Dejonghe, Liesbet Van der Perre
2010DACExploiting finite precision information to guide data-flow mapping.David Novo, Min Li, Robert Fasthuber, Praveen Raghavan, Francky Catthoor
2009ASPDACSystematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2009DSDCompilation Technique for Loop Overhead Minimization.Nikolas Kroupis, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Dimitrios Soudris
2008VLSIDEnergy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor.Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest
2007DATEVery wide register: an asymmetric register file organization for low power embedded processors.Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal
2007ISCASReduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.Praveen Raghavan, Jos L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa Lpez-Vallejo
2006DATEDistributed loop controller architecture for multi-threading in uni-threaded VLIW processors.Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest