Raimund Ubar
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
72
Venues
11
Active years
1994–2025
Best venue rank
C
Where they publish
Papers
72 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ETS | European Test Symposium Teams: an Anniversary Snapshot. | Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilrd Enyedi, Iulia Stefan, Ovidiu Stan, Cosmina Corches, Zebo Peng, Petru Eles, Rolf Drechsler, S. Eggersgl, Grschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Po-Yao Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, Stefano Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, Patrick Girard, Marcello Traiola, Arnaud Virazel, Fernando Fernandes dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letcia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, Fabian Luis Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, Anurup Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand |
| 2021 | DSD | Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules. | Maksim Jenihhin, Adeboye Stephen Oyeniran, Jaan Raik, Raimund Ubar |
| 2020 | DSD | Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors. | Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik |
| 2020 | IOLTS | Representing Gate-Level SET Faults by Multiple SEU Faults at RTL. | Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer |
| 2019 | DDECS | New categories of Safe Faults in a processor-based Embedded System. | Cemil Cem Grsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar |
| 2019 | DSD | True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital Circuits. | Raimund Ubar, Lembit Jrimgi, Adeniyi Olanrewaju Adekoya, Maksim Jenihhin |
| 2019 | ETS | High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. | Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Grsoy, Jaan Raik |
| 2019 | IOLTS | Application Specific True Critical Paths Identification in Sequential Circuits. | Lembit Jrimgi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Adeboye Stephen Oyeniran |
| 2018 | DDECS | Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells. | Siavoosh Payandeh Azad, Adeboye Stephen Oyeniran, Raimund Ubar |
| 2018 | ISCAS | Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation. | Adeboye Stephen Oyeniran, Siavoosh Payandeh Azad, Raimund Ubar |
| 2017 | DDECS | From online fault detection to fault management in Network-on-Chips: A ground-up approach. | Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Nevin George, Stephen Adeboye Oyeniran, Tsotne Putkaradze, Apneet Kaur, Jaan Raik, Gert Jervan, Raimund Ubar, Thomas Hollstein |
| 2017 | DDECS | A scalable technique to identify true critical paths in sequential circuits. | Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik |
| 2016 | DDECS | High-level modeling and testing of multiple control faults in digital systems. | Artjom Jasnetski, Stephen Adeboye Oyeniran, Anton Tsertov, Mario Schlzel, Raimund Ubar |
| 2015 | DATE | Fault simulation with parallel exact critical path tracing in multiple core environment. | Maksim Gorev, Raimund Ubar, Sergei Devadze |
| 2015 | DDECS | New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. | Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar |
| 2015 | DDECS | SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic. | Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Thiago Copetti, Fabian Vargas, Letcia Maria Bolzani Phls |
| 2015 | DSD | Double Phase Fault Collapsing with Linear Complexity in Digital Circuits. | Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Galina Josifovska, Stephen Adeboye Oyeniran |
| 2015 | ISCAS | Combinational fault simulation in sequential circuits. | Raimund Ubar, Jaak Kousaar, Maksim Gorev, Sergei Devadze |
| 2014 | DDECS | Lower bounds of the size of Shared Structurally Synthesized BDDs. | Raimund Ubar, Dmitri Mironov |
| 2014 | DSD | Critical Path Tracing Based Simulation of Transition Delay Faults. | Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik |
| 2014 | ETS | Logic simulation and fault collapsing with shared structurally synthesized bdds. | Dmitri Mironov, Raimund Ubar, Jaan Raik |
| 2013 | DSD | Identifying NBTI-Critical Paths in Nanoscale Logic. | Raimund Ubar, Fabian Vargas, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Letcia Maria Bolzani Poehls |
| 2012 | DDECS | Multiple stuck-at-fault detection theorem. | Raimund Ubar, Sergei Kostin, Jaan Raik |
| 2012 | DSD | How to Prove that a Circuit is Fault-Free? | Raimund Ubar, Sergei Kostin, Jaan Raik |
| 2012 | ETS | Combining dynamic slicing and mutation operators for ESL correction. | Urmas Repinski, Hanno Hantson, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Giuseppe Di Guglielmo, Graziano Pravadelli, Franco Fummi |
| 2011 | DDECS | Probabilistic equivalence checking based on high-level decision diagrams. | Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik |
| 2011 | DDECS | Defect-oriented module-level fault diagnosis in digital circuits. | Sergei Kostin, Raimund Ubar, Jaan Raik |
| 2011 | DSD | SoC and Board Modeling for Processor-Centric Board Testing. | Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze |
| 2011 | ETS | Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. | Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara |
| 2010 | DATE | Parallel X-fault simulation with critical path tracing technique. | Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman |
| 2010 | DDECS | Constraint-based test pattern generation at the Register-Transfer Level. | Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko |
| 2010 | DSD | Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. | Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman |
| 2010 | IDC | Collaborative Distributed Fault Simulation for Digital Electronic Circuits. | Eero Ivask, Sergei Devadze, Raimund Ubar |
| 2010 | ISCAS | Fault collapsing with linear complexity in digital circuits. | Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman |
| 2010 | ISM | Remote and Virtual Laboratories in Problem-Based Learning Scenarios. | Heinz-Dietrich Wuttke, Raimund Ubar, Karsten Henke |
| 2009 | DSD | Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems. | Raimund Ubar, Sergei Kostin, Jaan Raik |
| 2009 | ITC | Fast extended test access via JTAG and FPGAs. | Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar |
| 2008 | ASPDAC | Parallel fault backtracing for calculation of fault coverage. | Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman |
| 2008 | DDECS | Web-Based Framework for Parallel Distributed Test. | Eero Ivask, Jaan Raik, Raimund Ubar |
| 2008 | DDECS | Calculation of LFSR Seed and Polynomial Pair for BIST Applications. | Artur Jutman, Anton Tsertov, Raimund Ubar |
| 2008 | DDECS | Code Coverage Analysis using High-Level Decision Diagrams. | Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee |
| 2008 | DSD | Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. | Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz |
| 2008 | ETS | Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. | Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar |
| 2008 | IDC | Distributed Approach for Genetic Test Generation in the Field of Digital Electronics. | Eero Ivask, Jaan Raik, Raimund Ubar |
| 2007 | DDECS | Layout to Logic Defect Analysis for Hierarchical Test Generation. | Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski |
| 2007 | DSD | Hybrid BIST Optimization Using Reseeding and Test Set Compaction. | Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar |
| 2007 | DSD | Hierarchical Identification of Untestable Faults in Sequential Circuits. | Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus |
| 2007 | DSD | Fault Diagnosis in Integrated Circuits with BIST. | Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evartson, Harri Lensen |
| 2007 | ETS | Test Configurations for Diagnosing Faulty Links in NoC Switches. | Jaan Raik, Raimund Ubar, Vineeth Govind |
| 2007 | ETS | Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. | Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman |
| 2006 | DSD | Off-Line Testing of Delay Faults in NoC Interconnects. | Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng |
| 2006 | DSD | High-Level Decision Diagram based Fault Models for Targeting FSMs. | Jaan Raik, Raimund Ubar, Taavi Viilukas |
| 2005 | DSD | An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. | Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov |
| 2005 | DSD | Improved Fault Emulation for Synchronous Sequential Circuits. | Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar |
| 2005 | DSD | Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. | Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz |
| 2005 | EDCC | Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. | Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman |
| 2005 | ETS | DOT: new deterministic defect-oriented ATPG tool. | Jaan Raik, Raimund Ubar, Joachim Sudbrock, Wieslaw Kuzmicz, Witold A. Pleskacz |
| 2005 | ETS | Energy minimization for hybrid BIST in a system-on-chip test environment. | Raimund Ubar, Tatjana Shchenova, Gert Jervan, Zebo Peng |
| 2003 | DSD | Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. | Vladimir Hahanov, Raimund Ubar, Stanley Hyduke |
| 2002 | DATE | Internet-Based Collaborative Test Generation with MOSCITO. | Andr Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibkov, Elena Gramatov |
| 2002 | DSD | Integrated Design and Test Generation Under Internet Based Environment MOSCITO. | Andr Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatov, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng |
| 2001 | DATE | Timing simulation of digital circuits with binary decision diagrams. | Raimund Ubar, Artur Jutman, Zebo Peng |
| 2001 | DSD | Fast Test Cost Calculation for Hybrid BIST in Digital Systems. | Elmet Orasson, Rein Raidma, Raimund Ubar, Gert Jervan, Zebo Peng |
| 2000 | DATE | Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. | Adam Morawiec, Raimund Ubar, Jaan Raik |
| 2000 | ETS | Hierarchical defect-oriented fault simulation for digital circuits. | Mykola Blyzniuk, T. Cibkov, Elena Gramatov, Wieslaw Kuzmicz, M. Lobur, Witold A. Pleskacz, Jaan Raik, Raimund Ubar |
| 2000 | ISCAS | Back-tracing and event-driven techniques in high-level simulation with decision diagrams. | Raimund Ubar, Jaan Raik, Adam Morawiec |
| 1999 | DATE | Sequential Circuit Test Generation Using Decision Diagram Models. | Jaan Raik, Raimund Ubar |
| 1999 | DATE | Cycle-based Simulation with Decision Diagrams. | Raimund Ubar, Jaan Raik, Adam Morawiec |
| 1999 | ETS | High-level path activation technique to speed up sequential circuit test generation. | Jaan Raik, Raimund Ubar |
| 1997 | DATE | A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. | Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Raimund Ubar |
| 1996 | EDCC | Multi-Level Test Generation and Fault Diagnosis for Finite State Machines. | Raimund Ubar, Marina Brik |
| 1994 | EDCC | Test Generation for Digital Systems Based on Alternative Graphs. | Raimund Ubar |