Salvador Mir
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
64
Venues
11
Active years
1994–2023
Best venue rank
A*
Where they publish
Papers
64 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2023 | ISCAS | A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell. | Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragn |
| 2022 | ETS | Special Session on RF/5G Test. | William R. Eisenstadt, Mark Roos, Devin Morris, Jos Luis Gonzlez-Jimnez, Christopery Mounet, Manuel J. Barragn, Gildas Lger, Florent Cilici, Estelle Lauga-Larroze, Salvador Mir, Sylvain Bourdel, Marc Margalef-Rovira, Issa Alaji, Haitham Ghanem, Guillaume Ducournau, Christophe Gaquire |
| 2022 | VTS | Innovative Practices Track: Innovative Analog Circuit Testing Technologies. | Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragn, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa |
| 2021 | ETS | Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation. | Ankush Mamgain, Manuel J. Barragn, Salvador Mir |
| 2020 | ETS | On-chip reduced-code static linearity test of V | Renato S. Feitoza, Manuel J. Barragn, Antonio J. Gins, Salvador Mir |
| 2020 | IOLTS | A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. | Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel J. Barragn, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Rgis Leveugle, Salvador Mir |
| 2019 | DATE | On the use of causal feature selection in the context of machine-learning indirect test. | Manuel J. Barragn, Gildas Lger, Florent Cilici, Estelle Lauga-Larroze, Sylvain Bourdel, Salvador Mir |
| 2019 | ETS | A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology. | Hani Malloug, Manuel J. Barragn, Salvador Mir |
| 2019 | ISCAS | Yield Recovery of mm-Wave Power Amplifiers using Variable Decoupling Cells and One-Shot Statistical Calibration. | Florent Cilici, Manuel J. Barragn, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel, Gildas Lger |
| 2018 | ETS | Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits. | Florent Cilici, Manuel J. Barragn, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel |
| 2018 | IOLTS | Reduced-code static linearity test of SAR ADCs using a built-in incremental ∑Δ converter. | Renato S. Feitoza, Manuel J. Barragn, Salvador Mir, Daniel Dzahini |
| 2017 | ETS | Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology. | Hani Malloug, Manuel J. Barragan Asian, Salvador Mir, Laurent Basteres, Herv Le Gall |
| 2017 | ETS | Mixed-signal BIST computation offloading using IEEE 1687. | Michele Portolan, Manuel J. Barragn, Rshdee Alhakim, Salvador Mir |
| 2017 | VTS | Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs. | Guillaume Renaud, Marc Margalef-Rovira, Manuel J. Barragn, Salvador Mir |
| 2016 | DATE | Built-in test of millimeter-Wave circuits based on non-intrusive sensors. | Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld |
| 2016 | ETS | Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. | Antonio J. Gins, Eduardo J. Peralas, Gildas Lger, Adoracin Rueda, Guillaume Renaud, Manuel J. Barragn, Salvador Mir |
| 2015 | ETS | High frequency jitter estimator for SoCs. | Herv Le Gall, Rshdee Alhakim, Miroslav Valka, Salvador Mir, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu |
| 2015 | ITC | Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times. | Haralampos-G. D. Stratigopoulos, Manuel J. Barragn, Salvador Mir, Herv Le Gall, Neha Bhargava, Ankur Bal |
| 2015 | VTS | Horizontal-FPN fault coverage improvement in production test of CMOS imagers. | Richun Fei, Jocelyn Moreau, Salvador Mir, Alexis Marcellin, C. Mandier, E. Huss, G. Palmigiani, P. Vitrou, Thomas Droniou |
| 2014 | IOLTS | Solutions for the self-adaptation of communicating systems in operation. | Martin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azas, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzerho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G. D. Stratigopoulos |
| 2013 | ETS | Efficient minimization of test frequencies for linear analog circuits. | Mohand Bentobache, Ahcne Bounceur, Reinhardt Euler, Yann Kieffer, Salvador Mir |
| 2013 | ITC | True non-intrusive sensors for RF built-in test. | Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir |
| 2013 | ITC | Fault modeling and diagnosis for nanometric analog circuits. | Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir |
| 2013 | VTS | Defect-oriented non-intrusive RF test using on-chip temperature sensors. | Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Josep Altet |
| 2013 | VTS | Reduced code linearity testing of pipeline adcs in the presence of noise. | Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Herv Naudet, Gerard Bret |
| 2012 | DATE | Testing RF circuits with true non-intrusive built-in sensors. | Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Josep Altet |
| 2012 | ETS | Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs. | Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Herv Naudet, Christophe Forel |
| 2012 | ITC | Experiences with non-intrusive sensors for RF built-in test. | Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma |
| 2012 | VTS | Analog/RF test ordering in the early stages of production testing. | Nourredine Akkouche, Salvador Mir, Emmanuel Simeu, Mustapha Slamani |
| 2010 | DATE | Fault diagnosis of analog circuits based on machine learning. | Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir |
| 2010 | ETS | Sensors for built-in alternate RF test. | Louay Abdallah, Haralampos-G. D. Stratigopoulos, Christophe Kelma, Salvador Mir |
| 2010 | ETS | Defect filter for alternate RF test. | Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev |
| 2010 | ICCAD | Analog test metrics estimates with PPM accuracy. | Haralampos-G. D. Stratigopoulos, Salvador Mir |
| 2010 | VTS | Ordering of analog specification tests based on parametric defect level estimation. | Nourredine Akkouche, Salvador Mir, Emmanuel Simeu |
| 2010 | VTS | Density estimation for analog/RF test problem solving. | Salvador Mir, Haralampos-G. D. Stratigopoulos, Ahcne Bounceur |
| 2009 | DATE | Enrichment of limited training sets in machine-learning-based analog/RF test. | Haralampos-G. D. Stratigopoulos, Salvador Mir, Yiorgos Makris |
| 2009 | ETS | Defect Filter for Alternate RF Test. | Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev |
| 2009 | ICCD | Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study. | Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir |
| 2009 | VTS | Experimental Validation of a BIST Techcnique for CMOS Active Pixel Sensors. | Livier Lizarraga, Salvador Mir, Gilles Sicard |
| 2008 | DATE | A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation. | Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, Salvador Mir |
| 2007 | DATE | Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model. | Jeanne Tongbong, Salvador Mir, Jean-Louis Carbonro |
| 2007 | IOLTS | Envelope Detection Based Transition Time Supervision for Online Testing of RF MEMS Switches. | Emmanuel Simeu, Salvador Mir, R. Kherreddine, Hoang Nam Nguyen |
| 2007 | ITC | A stereo audio Σ∑ ADC architecture with embedded SNDR self-test. | Lus Rolndez, Salvador Mir, Jean-Louis Carbonro, Dimitri Goguet, Nabil Chouba |
| 2006 | DATE | Pseudorandom functional BIST for linear and nonlinear MEMS. | Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcne Bounceur |
| 2006 | VTS | A SNDR BIST for Sigma-Delta Analogue-to-Digital Converters. | Lus Rolndez, Salvador Mir, Ahcne Bounceur, Jean-Louis Carbonro |
| 2005 | DATE | Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach. | Rabeb Kheriji, V. Danelon, Jean-Louis Carbonro, Salvador Mir |
| 2005 | ETS | Evaluation of impulse response-based BIST techniques for MEMS in the presence of weak nonlinearities. | Achraf Dhayni, Salvador Mir, Libor Rufer |
| 2004 | DATE | A 0.18 m CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns. | Lus Rolndez, Salvador Mir, Guillaume Prenat, Ahcne Bounceur |
| 2004 | ETS | Mems built-in-self-test using MLS. | Achraf Dhayni, Salvador Mir, Libor Rufer |
| 2004 | VLSID | On-chip testing of embedded transducers. | Salvador Mir, Libor Rufer, Bernard Courtois |
| 2003 | ASPDAC | An implementation of memory-based on-chip analogue test signal generation. | Salvador Mir, Lus Rolndez, Christian Domigues, Libor Rufer |
| 2003 | IOLTS | On-Line Testable Decimation Filter Design for AMS Systems. | Mohammad A. Naal, Emmanuel Simeu, Salvador Mir |
| 2002 | VTS | SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? | Salvador Mir, H. Bederr, R. D. (Shawn) Blanton, Hans G. Kerkhoff, H. J. Klim |
| 2001 | VTS | Electrically Induced Stimuli For MEMS Self-Test. | Benot Charlot, Salvador Mir, Fabien Parrain, Bernard Courtois |
| 1999 | ETS | Extending fault-based testing to microelectromechanical systems. | Salvador Mir, Benot Charlot, Bernard Courtois |
| 1999 | ITC | Fault modeling of suspended thermal MEMS. | Benot Charlot, Salvador Mir, rika F. Cota, Marcelo Lubaszewski, Bernard Courtois |
| 1999 | VLSID | Design and Test of MEMs. | Bernard Courtois, Jean-Michel Karam, Salvador Mir, Marcelo Lubaszewski, Vladimr Szkely, Mrta Rencz, Klaus Hofmann, Manfred Glesner |
| 1998 | DATE | Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems. | Salvador Mir, Adoracin Rueda, Diego Vzquez, Jos Luis Huertas |
| 1998 | ITC | Failure mechanisms and fault classes for CMOS-compatible microelectromechanical systems. | A. Castillejo, D. Veychard, Salvador Mir, Jean-Michel Karam, Bernard Courtois |
| 1997 | DAC | SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. | Salvador Mir, Adoracin Rueda, Thomas Olbrich, Eduardo J. Peralas, Jos Luis Huertas |
| 1996 | DATE | Automatic Test Generation for Maximal Diagnosis of Linear Analogue Circuits. | Salvador Mir, Bernard Courtois, Marcelo Lubaszewski, Vladimir Kolarik |
| 1996 | ICCAD | ABILBO: Analog BuILt-in Block Observer. | Marcelo Lubaszewski, Salvador Mir, Leandro Pulz |
| 1995 | DATE | Mixed-signal circuits and boards for high safety applications. | Marcelo Lubaszewski, Vladimir Kolarik, Salvador Mir, C. Nielsen, Bernard Courtois |
| 1994 | ICCAD | Built-in self-test and fault diagnosis of fully differential analogue circuits. | Salvador Mir, Vladimir Kolarik, Marcelo Lubaszewski, C. Nielsen, Bernard Courtois |