| 2018 | DATE | A fast and effective lookahead and fractional search based scheduling algorithm for high-level synthesis. | Shantanu Dutt, Ouwen Shi |
| 2015 | ICCAD | Communication Scheduling and Buslet Synthesis for Low-Interconnect HLS Designs. | Enzo Tartaglione, Shantanu Dutt |
| 2010 | ICCAD | Timing yield optimization via discrete gate sizing using globally-informed delay PDFs. | Shantanu Dutt, Huan Ren |
| 2008 | ICCAD | Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure. | Huan Ren, Shantanu Dutt |
| 2007 | ICCD | Constraint satisfaction in incremental placement with application to performance optimization under power constraints. | Huan Ren, Shantanu Dutt |
| 2006 | DATE | Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations. | Shantanu Dutt, Hasan Arslan |
| 2006 | DATE | Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults. | Vishal Suthar, Shantanu Dutt |
| 2006 | ICCAD | A network-flow approach to timing-driven incremental placement for ASICs. | Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar |
| 2006 | VTS | Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions. | Vishal Suthar, Shantanu Dutt |
| 2004 | DAC | Efficient on-line testing of FPGAs with provable diagnosabilities. | Vinay Verma, Shantanu Dutt, Vishal Suthar |
| 2004 | FPGA | Roving testing using new built-in-self-tester designs for FPGAs. | Vinay Verma, Shantanu Dutt |
| 2004 | ICCD | A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits. | Hasan Arslan, Shantanu Dutt |
| 2003 | ICCD | ROAD : An Order-Impervious Optimal Detailed Router for FPGAs. | Hasan Arslan, Shantanu Dutt |
| 2002 | DAC | Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control. | Ke Zhong, Shantanu Dutt |
| 2001 | ICCAD | A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs. | Vinay Verma, Shantanu Dutt |
| 2000 | ICCAD | Effective Partition-Driven Placement with Simultaneous Level Processing and a Global Net Views. | Ke Zhong, Shantanu Dutt |
| 1999 | ICCAD | Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays. | Shantanu Dutt, Vimalvel Shanmugavel, Steven Trimberger |
| 1997 | ICCAD | Partitioning around roadblocks: tackling constraints with intermediate relaxations. | Shantanu Dutt, Halim Theny |
| 1996 | DAC | A Probability-Based Approach to VLSI Circuit Partitioning. | Shantanu Dutt, Wenyong Deng |
| 1996 | ICCAD | VLSI circuit partitioning by cluster-removal using iterative improvement techniques. | Shantanu Dutt, Wenyong Deng |
| 1996 | ICCD | Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. | Fran Hancheck, Shantanu Dutt |
| 1996 | ICS | Are There Advantages to High-Dimension Architectures? Analysis of | Shantanu Dutt, Nam Trinh |
| 1996 | VLSID | Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs. | Fran Hanchek, Shantanu Dutt |
| 1993 | ICCAD | New faster Kernighan-Lin-type graph-partitioning algorithms. | Shantanu Dutt |