| 2026 | FCCM | Enabling Context-Switchable Monolithic 3D FPGA Design Using Bistable Ferroelectric Inverters. | Faaiq G. Waqar, Matthew Chen, Zifan He, Zishen Wan, Minji Shon, Wei-Hsing Huang, Jason Cong, Shimeng Yu |
| 2026 | ISCA | Omelet: A Packaging-Aware Hierarchical Interconnect Simulator for 2.5D/3D Chiplet Architectures. | Jiho Kim, Danish Baig, Faaiq Waqar, Ashita Victor, Shimeng Yu, Muhannad S. Bakir, Cong Hao |
| 2026 | VLSID | ThermLeT: Transformer-Based Temperature Prediction for 2.5D Chiplet Architecture. | Varun Darshana Parekh, Anusha Devulapally, Sivani Devarapalli, Cassius Henderson, Shimeng Yu, Vijaykrishnan Narayanan |
| 2025 | ASPDAC | Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference. | Wei-Hsing Huang, Jianwei Jia, Yuyao Kong, Faaiq G. Waqar, Tai-Hao Wen, Meng-Fan Chang, Shimeng Yu |
| 2025 | DAC | Monolithic 3D FPGA Design and Synthesis with Back-End-of-Line Configuration Memories. | Faaiq G. Waqar, Jiahao Zhang, Anni Lu, Zifan He, Jason Cong, Shimeng Yu |
| 2025 | DATE | Runtime Security Analysis of Monolithic 3D Embedded DRAM with Oxide-Channel Transistor. | Eduardo Ortega, Jungyoun Kwak, Shimeng Yu, Krishnendu Chakrabarty |
| 2025 | ICCAD | FeNOMS: Enhancing Open Modification Spectral Library Search with In-Storage Processing on Ferroelectric NAND (FeNAND) Flash. | Sumukh Pinge, Ashkan Moradifirouzabadi, Keming Fan, Prasanna Venkatesan Ravindran, Tanvir H. Pantha, Po-Kai Hsu, Zheyu Li, Weihong Xu, Zihan Xia, Flavio Ponzina, Winston Chern, Taeyoung Song, Priyankka Gundlapudi Ravikumar, Mengkun Tian, Lance Fernandes, Huy Tran, Hari Jayasankar, Hang Chen, Chinsung Park, Amrit Garlapati, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Duygu Kuzum, Shimeng Yu, Sourav Dutta, Asif Khan, Tajana Rosing, Mingu Kang |
| 2025 | ISCAS | Digital Compute-in-Memory Ising Annealer with Ferroelectric Capacitor-Based nvSRAM for Combinatorial Optimization Problems. | Yuyao Kong, Jianwei Jia, Anni Lu, Faaiq G. Waqar, Yuan-Chun Luo, Hai Li, Ian A. Young, Shimeng Yu |
| 2025 | MICRO | Stratum: System-Hardware Co-Design with Tiered Monolithic 3D-Stackable DRAM for Efficient MoE Serving. | Yue Pan, Zihan Xia, Po-Kai Hsu, Lanxiang Hu, Hyungyo Kim, Janak Sharda, Minxuan Zhou, Nam Sung Kim, Shimeng Yu, Tajana Rosing, Mingu Kang |
| 2024 | ASPDAC | A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators. | Yuan-Chun Luo, James Read, Anni Lu, Shimeng Yu |
| 2024 | DAC | Digital CIM with Noisy SRAM Bit: A Compact Clustered Annealer for Large-Scale Combinatorial Optimization. | Anni Lu, Junmo Lee, Yuan-Chun Luo, Hai Li, Ian A. Young, Shimeng Yu |
| 2024 | ISCAS | Monolithic 3D Transposable 3T Embedded DRAM with Back-end-of-line Oxide Channel Transistor. | Jungyoun Kwak, Gihun Choe, Junmo Lee, Shimeng Yu |
| 2023 | DATE | PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration. | Wangxin He, Jian Meng, Sujan Kumar Gonugondla, Shimeng Yu, Naresh R. Shanbhag, Jae-sun Seo |
| 2023 | DATE | RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers. | Wantong Li, Yandong Luo, Shimeng Yu |
| 2023 | IJCNN | CLUE: Cross-Layer Uncertainty Estimator for Reliable Neural Perception using Processing-in-Memory Accelerators. | Minah Lee, Anni Lu, Mandovi Mukherjee, Shimeng Yu, Saibal Mukhopadhyay |
| 2023 | ISCAS | Enabling Long-Term Robustness in RRAM-based Compute-In-Memory Edge Devices. | James Read, Wantong Li, Shimeng Yu |
| 2021 | DATE | A FeRAM based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training. | Yandong Luo, Yuan-Chun Luo, Shimeng Yu |
| 2021 | DATE | A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator. | Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu |
| 2021 | ISCAS | Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning. | Shanshi Huang, Xiaochen Peng, Hongwu Jiang, Yandong Luo, Shimeng Yu |
| 2021 | ISCAS | Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator. | Panni Wang, Xiaochen Peng, Wriddhi Chakraborty, Asif Khan, Suman Datta, Shimeng Yu |
| 2020 | ASPDAC | Benchmark Non-volatile and Volatile Memory Based Hybrid Precision Synapses for In-situ Deep Neural Network Training. | Yandong Luo, Shimeng Yu |
| 2020 | DAC | A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. | Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu |
| 2020 | DATE | Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories. | Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu |
| 2020 | ICCAD | XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption. | Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu |
| 2020 | ISCAS | MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture. | Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Shimeng Yu |
| 2020 | ISCAS | A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out. | Yandong Luo, Xiaochen Peng, Ryan Hatcher, Titash Rakshit, Jorge Kittl, Mark S. Rodder, Jae-Sun Seo, Shimeng Yu |
| 2019 | DAC | Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis. | Wenqiang Zhang, Xiaochen Peng, Huaqiang Wu, Bin Gao, Hu He, Youhui Zhang, Shimeng Yu, He Qian |
| 2019 | ISCAS | Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture. | Xiaochen Peng, Rui Liu, Shimeng Yu |
| 2019 | ISCAS | Design Space Exploration of Ovonic Threshold Switch (OTS) for Sub-Threshold Read Operation in Cross-Point Memory Arrays. | Jiyong Woo, Shimeng Yu |
| 2018 | ASPDAC | Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. | Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu |
| 2018 | DAC | Parallelizing SRAM arrays with customized bit-cell for binary neural networks. | Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu |
| 2018 | DATE | XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. | Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu |
| 2018 | ISCAS | Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic Computing. | Jiyong Woo, Xiaochen Peng, Shimeng Yu |
| 2018 | VTS | Special session on reliability and vulnerability of neuromorphic computing systems. | Shimeng Yu, Chenchen Liu, Wujie Wen, Yiran Chen |
| 2017 | ISCAS | Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array. | Rui Liu, Pai-Yu Chen, Shimeng Yu |
| 2016 | DATE | MNSIM: Simulation platform for memristor-based neuromorphic computing system. | Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang |
| 2016 | ICCAD | Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing. | Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu |
| 2016 | ISCAS | Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing. | Pai-Yu Chen, Shimeng Yu |
| 2016 | ISCAS | Design of a reliable RRAM-based PUF for compact hardware security primitives. | Ayush Shrivastava, Pai-Yu Chen, Yu Cao, Shimeng Yu, Chaitali Chakrabarti |
| 2015 | ASPDAC | Technological exploration of RRAM crossbar array for matrix-vector multiplication. | Peng Gu, Boxun Li, Tianqi Tang, Shimeng Yu, Yu Cao, Yu Wang, Huazhong Yang |
| 2015 | DATE | Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. | Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu |
| 2015 | HPCA | Overcoming the challenges of crossbar resistive memory architectures. | Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie |
| 2015 | ICCAD | Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. | Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu |
| 2015 | ICCD | Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings. | Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti |
| 2015 | ISCAS | Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design. | Scott Zuloaga, Rui Liu, Pai-Yu Chen, Shimeng Yu |
| 2014 | ASPDAC | Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture. | Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie |
| 2014 | ICCAD | Architecting 3D vertical resistive memory for next-generation storage systems. | Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie |
| 2014 | ISCAS | Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture. | Jinfeng Kang, Bin Gao, Bing Chen, Peng Huang, Feifei Zhang, Xiaoyan Liu, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong, Shimeng Yu |
| 2014 | ISCAS | Orientation classification by a winner-take-all network with oxide RRAM based synaptic devices. | Shimeng Yu |
| 2014 | ISCAS | Overview of resistive switching memory (RRAM) switching mechanism and device modeling. | Shimeng Yu |
| 2014 | ISCAS | Design guidelines for 3D RRAM cross-point architecture. | Shimeng Yu, Yexin Deng, Bin Gao, Peng Huang, Bing Chen, Xiaoyan Liu, Jinfeng Kang, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong |
| 2014 | ISCAS | Design considerations of synaptic device for neuromorphic computing. | Shimeng Yu, Duygu Kuzum, H.-S. Philip Wong |