| 2023 | VTS | Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. | Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen |
| 2023 | VTS | Silent Data Errors: Sources, Detection, and Modeling. | Adit D. Singh, Sreejit Chakravarty, George Papadimitriou, Dimitris Gizopoulos |
| 2023 | VTS | IP Session on Chiplet: Design, Assembly, and Test. | Bapi Vinnakota, Jaber Derakhshandeh, Eric Beyne, Erik Jan Marinissen, Sreejit Chakravarty |
| 2022 | VTS | Special Session: A Call to Standardize Chip-let Interconnect Testing. | Sreejit Chakravarty |
| 2020 | VTS | Internal I/O Testing: Definition and a Solution. | Sreejit Chakravarty, Fei Su, Indira A. Gohad, Sudheer V. Bandana, B. S. Adithya, Wei Ming Lim |
| 2019 | VTS | A Comparative Study of Pre-bond TSV Test Methodologies. | Sourav Das, Fei Su, Sreejit Chakravarty |
| 2018 | ITC | A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing. | Sourav Das, Fei Su, Sreejit Chakravarty |
| 2018 | VTS | Innovative practices on memory test practice. | M. Casarsa, Gurgen Harutyunyan, Kaitlyn Chen, Ramesh Sharma, Giri Podichetty, Martin Keim, Sreejit Chakravarty, Ramesh C. Tekumalla |
| 2018 | VTS | Innovative practices on functional testing and fault simulation for FuSa. | Anandh Krishnan, John van Gelder, Mayukh Bhattacharya, Sreejit Chakravarty, Prashant Goteti |
| 2017 | VTS | Innovative practices session 6C DFT for functional safety. | Prashant Goteti, Sreejit Chakravarty |
| 2013 | VTS | Innovative practices session 2C: Memory test. | Charutosh Dixit, Ramesh C. Tekumalla, Sreejit Chakravarty, Manuel d'Abreu, Zhuoyu Bao, Concetta Riccobene |
| 2012 | VTS | Silicon evaluation of faster than at-speed transition delay tests. | Sreejit Chakravarty, Narendra Devta-Prasanna, Arun Gunda, Junxia Ma, Fan Yang, H. Guo, R. Lai, D. Li |
| 2012 | VTS | A novel method for fast identification of peak current during test. | Wei Zhao, Sreejit Chakravarty, Junxia Ma, Narendra Devta-Prasanna, Fan Yang, Mohammad Tehranipoor |
| 2011 | ITC | Optimal manufacturing flow to determine minumum operating voltage. | Sreejit Chakravarty, Binh Dang, Darcy Escovedo, A. J. Haas |
| 2011 | VTS | Power-safe test application using an effective gating approach considering current limits. | Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty |
| 2010 | ITC | Testing of latch based embedded arrays using scan tests. | Fan Yang, Sreejit Chakravarty |
| 2010 | VTS | Special session 11C: Hot topic design consideration and silicon evaluation of on-chip monitors. | Sreejit Chakravarty |
| 2010 | VTS | Impact of multiple input switching on delay test under process variation. | Sean H. Wu, Sreejit Chakravarty, Li-C. Wang |
| 2009 | ASPDAC | Path selection for monitoring unexpected systematic timing effects. | Nicholas Callegari, Pouria Bastani, Li-C. Wang, Sreejit Chakravarty, Alexander Tetelbaum |
| 2009 | ASPDAC | Detectability of internal bridging faults in scan chains. | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
| 2008 | IOLTS | An Enhanced Logic BIST Architecture for Online Testing. | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
| 2008 | ITC | Detection of Internal Stuck-open Faults in Scan Chains. | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
| 2008 | VTS | An Industrial Case Study of Sticky Path-Delay Faults. | I-De Huang, Yi-Shing Chang, Sandeep K. Gupta, Sreejit Chakravarty |
| 2008 | VTS | On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
| 2006 | ITC | Exact At-speed Delay Fault Grading in Sequential Circuits. | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi |
| 2006 | ITC | A Study of Implication Based Pseudo Functional Testing. | Manan Syal, Kameshwar Chandrasekar, Vishnu C. Vimjam, Michael S. Hsiao, Yi-Shing Chang, Sreejit Chakravarty |
| 2006 | VTS | Path Delay Fault Simulation on Large Industrial Designs. | Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty |
| 2006 | VTS | Silicon Evaluation of Logic Proximity Bridge Patterns. | Eric N. Tran, Vishwashanth Kasulasrinivas, Sreejit Chakravarty |
| 2005 | DATE | Implicit and Exact Path Delay Fault Grading in Sequential Circuits. | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi |
| 2005 | ITC | Logic proximity bridges. | Eric N. Tran, Vamsee Krishna, Sujit T. Zachariah, Sreejit Chakravarty |
| 2005 | VTS | Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor. | Sreejit Chakravarty, Yi-Shing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, Cheryl Prunty, Eric W. Savage, Rehan Sheikh, Eric N. Tran, Khen Wee |
| 2005 | VTS | Transition Tests for High Performance Microprocessors. | Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee |
| 2004 | ITC | Defect Coverage Analysis of Partitioned Testing. | Sreejit Chakravarty, Eric W. Savage, Eric N. Tran |
| 2004 | ITC | Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. | Manan Syal, Michael S. Hsiao, Sreejit Chakravarty |
| 2003 | VTS | Efficient Implication - Based Untestable Bridge Fault Identifier. | Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, Sreejit Chakravarty |
| 2002 | ETS | Novel ATPG algorithms for transition faults. | Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran |
| 2002 | ITC | Experimental Evaluation of Scan Tests for Bridges. | Sreejit Chakravarty, Ankur Jain, Nandakumar Radhakrishnan, Eric W. Savage, Sujit T. Zachariah |
| 2002 | ITC | Techniques to Reduce Data Volume and Application Time for Transition Test. | Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran |
| 2002 | VTS | Fault Models for Speed Failures Caused by Bridges and Opens. | Sreejit Chakravarty, Ankur Jain |
| 2002 | VTS | Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms. | Sreejit Chakravarty, Kambiz Komeyli, Eric W. Savage, Michael J. Carruthers, Bret T. Stastny, Sujit T. Zachariah |
| 2001 | VLSID | A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits. | Sujit T. Zachariah, Sreejit Chakravarty |
| 2000 | DAC | A novel algorithm to extract two-node bridges. | Sujit T. Zachariah, Sreejit Chakravarty, Carl D. Roth |
| 2000 | ITC | An analysis of the delay defect detection capability of the ECR test method. | Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota |
| 2000 | ITC | A scalable and efficient methodology to extract two node bridges from large industrial circuits. | Sujit T. Zachariah, Sreejit Chakravarty |
| 1999 | ICCD | On Detecting Bridges Causing Timing Failures. | Sreenivas Mandava, Sreejit Chakravarty, Sandip Kundu |
| 1999 | VLSID | A Comparative Study of Pseudo Stuck-At and Leakage Fault Model. | Sujit T. Zachariah, Sreejit Chakravarty |
| 1999 | VTS | Techniques to Encode and Compress Fault Dictionaries. | Sreejit Chakravarty, Vinodh Gopal |
| 1998 | ITC | A new framework for generating optimal March tests for memory arrays. | Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty |
| 1998 | VLSID | Computing Stress Tests for Gate Oxide Shorts. | Vinay Dabholkar, Sreejit Chakravarty |
| 1997 | VTS | Using fault sampling to compute I | Yiming Gong, Sreejit Chakravarty |
| 1996 | VLSID | Fast Algorithms for Computer IDDQ Tests for Combination Circuits. | Paul J. Thadikaran, Sreejit Chakravarty |
| 1996 | VTS | A sampling technique for diagnostic fault simulation. | Sreejit Chakravarty |
| 1995 | DAC | Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. | Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel |
| 1995 | ICCAD | On adaptive diagnostic test generation. | Yiming Gong, Sreejit Chakravarty |
| 1995 | VLSID | Voting model based diagnosis of bridging faults in combinational circuits. | Sreejit Chakravarty, Yiming Gong |
| 1995 | VTS | Cyclic stress tests for full scan circuits. | Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel |
| 1994 | ITC | A Study of I | Sreejit Chakravarty, Paul J. Thadikaran |
| 1994 | VLSID | Untitled record | Sreejit Chakravarty, Sivaprakasam Suresh |
| 1994 | VTS | Diagnostic simulation of stuck-at faults in combinational circuits. | Sreejit Chakravarty, Yiming Gong |
| 1993 | DAC | An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits. | Sreejit Chakravarty, Yiming Gong |
| 1993 | VTS | Simulation and generation of I | Sreejit Chakravarty, Paul J. Thadikaran |
| 1992 | DAC | Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults. | Sreejit Chakravarty, Minsheng Liu |
| 1992 | VLSID | On Computing Tests for Bridging and Leakage Faults: Complexity Results and Universal Test Sets. | Sreejit Chakravarty |
| 1990 | DAC | On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract). | Sreejit Chakravarty |
| 1990 | ICPP | Heuristics for the MSC Problem for Serial and Shared-Memory Computers. | Ajay Shekhawat, Sreejit Chakravarty |
| 1989 | ITC | A Testable Realization of CMOS Combinational Circuits. | Sreejit Chakravarty |
| 1988 | ICPP | A Unified Approach to Designing Fault-Tolerant Processor Ensembles. | Sreejit Chakravarty, Shambhu J. Upadhyaya |
| 1986 | ITC | On the Computation of Detection Probability for Multiple Faults. | Sreejit Chakravarty, Harry B. Hunt III |