| 2025 | DAC | A Novel Covert Timing Channel for Cloud FPGAs. | Brian Udugama, Darshana Jayasinghe, Hassaan Saadat, Aleksandar Ignjatovic, Sri Parameswaran |
| 2025 | ICCAD | JitFilt: Mitigate Jitter-based Side Channel Analysis Attacks. | Darshana Jayasinghe, Yuanhua Zhong, Sri Parameswaran |
| 2024 | ASPDAC | Sensors for Remote Power Attacks: New Developments and Challenges. | Brian Udugama, Darshana Jayasinghe, Sri Parameswaran |
| 2024 | DATE | SEA: Sign-Separated Accumulation Scheme for Resource-Efficient DNN Accelerators. | Jing Gong, Hassaan Saadat, Haris Javaid, Hasindu Gamaarachchi, David Taubman, Sri Parameswaran |
| 2024 | DATE | Accelerating Chaining in Genomic Analysis Using RISC- V Custom Instructions. | Kisaru Liyanage, Hasindu Gamaarachchi, Hassaan Saadat, Tuo Li, Hiruna Samarakoon, Sri Parameswaran |
| 2024 | Tencon | Optimizing Convolutional Image Processing on RISC-V Using Branch Prediction on FPGA. | Mekala Bindu Bhargavi, Sujay Krishnan Subramanian, Sri Parameswaran, Soumya J. |
| 2023 | ASPDAC | FPGA Based Countermeasures against Side Channel Attacks on Block Ciphers. | Darshana Jayasinghe, Brian Udugama, Sri Parameswaran |
| 2023 | DAC | Invited: Algorithms and Architectures for Accelerating Long Read Sequence Analysis. | Hasindu Gamaarachchi, Kisaru Liyanage, Sri Parameswaran |
| 2022 | DAC | FaSe: fast selective flushing to mitigate contention-based cache timing attacks. | Tuo Li, Sri Parameswaran |
| 2022 | DAC | HWST128: complete memory safety accelerator on RISC-V with metadata compression. | Hsu-Kang Dow, Tuo Li, Sri Parameswaran |
| 2021 | ASPDAC | Approximate Computing for ML: State-of-the-art, Challenges and Visions. | Georgios Zervakis, Hassaan Saadat, Hussam Amrouch, Andreas Gerstlauer, Sri Parameswaran, Jrg Henkel |
| 2021 | DAC | SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V. | Hsu-Kang Dow, Tuo Li, William Miles, Sri Parameswaran |
| 2020 | ASPDAC | WEID: Worst-case Error Improvement in Approximate Dividers. | Hassaan Saadat, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran |
| 2020 | DATE | REALM: Reduced-Error Approximate Log-based Integer Multiplier. | Hassaan Saadat, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran |
| 2020 | FPL | LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs. | Farah Abid, Darshana Jayasinghe, Sompasong Somsavaddy, Sri Parameswaran |
| 2020 | ICCAD | Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping. | Ann Franchesca Laguna, Hasindu Gamaarachchi, Xunzhao Yin, Michael T. Niemier, Sri Parameswaran, Xiaobo Sharon Hu |
| 2020 | VLSID | A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units. | Hassaan Saadat, Tuo Li, Haris Javaid, Sri Parameswaran |
| 2019 | DAC | RFTC: Runtime Frequency Tuning Countermeasure Using FPGA Dynamic Reconfiguration to Mitigate Power Analysis Attacks. | Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran |
| 2019 | DAC | Approximate Integer and Floating-Point Dividers with Near-Zero Error Bias. | Hassaan Saadat, Haris Javaid, Sri Parameswaran |
| 2019 | DDECS | Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing. | Amin Malekpour, Roshan G. Ragel, Daniel Murphy, Aleksandar Ignjatovic, Sri Parameswaran |
| 2019 | ICCAD | SCRIP: Secure Random Clock Execution on Soft Processor Systems to Mitigate Power-based Side Channel Attacks. | Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran |
| 2018 | ASPDAC | MESGA: An MPSoC based embedded system solution for short read genome alignment. | Vikkitharan Gnanasambandapillai, Arash Bayat, Sri Parameswaran |
| 2018 | ASPDAC | CryptoBlaze: A partially homomorphic processor with multiple instructions and non-deterministic encryption support. | Florencia Irena, Daniel Murphy, Sri Parameswaran |
| 2017 | CASES | Hardware approximate computing: how, why, when and where? (special session). | Hassaan Saadat, Sri Parameswaran |
| 2017 | DAC | TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs. | Amin Malekpour, Roshan G. Ragel, Aleksandar Ignjatovic, Sri Parameswaran |
| 2017 | VLSID | NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks. | Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran |
| 2016 | ASPDAC | Improving tag generation for memory data authentication in embedded processor systems. | Tao Liu, Hui Guo, Sri Parameswaran, Xiaobo Sharon Hu |
| 2016 | DATE | RECORD: Reducing register traffic for checkpointing in embedded processors. | Tuo Li, Jude Angelo Ambrose, Sri Parameswaran |
| 2016 | ISCAS | The effect of amplitude resolution and mismatch on a digital-to-analog converter used for digital harmonic-cancelling sine-wave synthesis. | Pasindu Aluthwala, Neil Weste, Andrew Adams, Torsten Lehmann, Sri Parameswaran |
| 2015 | ASPDAC | Speeding up single pass simulation of PLRUt caches. | Josef Schneider, Jorgen Peddersen, Sri Parameswaran |
| 2015 | ASPDAC | ADAPT: An adaptive manycore methodology for software pipelined applications. | Xi Zhang, Haris Javaid, Muhammad Shafique, Jude Angelo Ambrose, Jrg Henkel, Sri Parameswaran |
| 2015 | CASES | QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks. | Darshana Jayasinghe, Aleksandar Ignjatovic, Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran |
| 2015 | DAC | SuperNet: multimode interconnect architecture for manycore chips. | Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jrg Henkel, Sri Parameswaran |
| 2015 | DATE | Malleable NoC: dark silicon inspired adaptable Network-on-Chip. | Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jrg Henkel, Sri Parameswaran |
| 2015 | DATE | Dynamic reconfigurable puncturing for secure wireless communication. | Liang Tang, Jude Angelo Ambrose, Akash Kumar, Sri Parameswaran |
| 2015 | DATE | E-pipeline: elastic hardware/software pipelines on a many-core fabric. | Xi Zhang, Haris Javaid, Muhammad Shafique, Jorgen Peddersen, Jrg Henkel, Sri Parameswaran |
| 2015 | ICCD | Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications. | Jude Angelo Ambrose, Yusuke Yachide, Kapil Batra, Jorgen Peddersen, Sri Parameswaran |
| 2015 | ICCD | RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory. | Su Myat Min Shwe, Kapil Batra, Yusuke Yachide, Jorgen Peddersen, Sri Parameswaran |
| 2015 | ISCAS | Design of a digital harmonic-cancelling sine-wave synthesizer with 100 MHz output frequency, 43.5 dB SFDR, and 2.26 mW power. | Pasindu Aluthwala, Neil Weste, Andrew Adams, Torsten Lehmann, Sri Parameswaran |
| 2015 | ISCAS | ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip. | Jude Angelo Ambrose, Nick Higgins, Mrinal Chakravarthy, Shivam Gargg, Tuo Li, Daniel Murphy, Aleksandar Ignjatovic, Sri Parameswaran |
| 2015 | VLSID | ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA. | Jude Angelo Ambrose, Tuo Li, Daniel Murphy, Shivam Gargg, Nick Higgins, Sri Parameswaran |
| 2014 | ASPDAC | SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs. | Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Alvin Labios, Yusuke Yachide |
| 2014 | ASPDAC | A scorchingly fast FPGA-based Precise L1 LRU cache simulator. | Josef Schneider, Jorgen Peddersen, Sri Parameswaran |
| 2014 | DAC | darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon. | Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jrg Henkel, Sri Parameswaran |
| 2014 | DAC | FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs. | Haris Javaid, Yusuke Yachide, Su Myat Min Shwe, Haseeb Bokhari, Sri Parameswaran |
| 2014 | DAC | MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis. | Josef Schneider, Jorgen Peddersen, Sri Parameswaran |
| 2014 | DATE | Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs. | Hong Chinh Doan, Haris Javaid, Sri Parameswaran |
| 2014 | DATE | Hardware-based fast exploration of cache hierarchies in application specific MPSoCs. | Isuru Nawinne, Josef Schneider, Haris Javaid, Sri Parameswaran |
| 2014 | ICCD | Advanced modes in AES: Are they safe from power analysis based side channel attacks? | Darshana Jayasinghe, Roshan G. Ragel, Jude Angelo Ambrose, Aleksandar Ignjatovic, Sri Parameswaran |
| 2014 | ISCAS | A simple digital architecture for a harmonic-cancelling sine-wave synthesizer. | Pasindu Aluthwala, Neil Weste, Andrew Adams, Torsten Lehmann, Sri Parameswaran |
| 2013 | ASPDAC | Multi-mode pipelined MPSoCs for streaming applications. | Haris Javaid, Daniel Witono, Sri Parameswaran |
| 2013 | ASPDAC | RExCache: Rapid exploration of unified last-level cache. | Su Myat Min, Haris Javaid, Sri Parameswaran |
| 2013 | DAC | RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors. | Tuo Li, Muhammad Shafique, Jude Angelo Ambrose, Semeen Rehman, Jrg Henkel, Sri Parameswaran |
| 2013 | DAC | XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs. | Su Myat Min, Haris Javaid, Sri Parameswaran |
| 2013 | DAC | Reconfigurable pipelined coprocessor for multi-mode communication transmission. | Liang Tang, Jude Angelo Ambrose, Sri Parameswaran |
| 2013 | DATE | CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors. | Tuo Li, Muhammad Shafique, Semeen Rehman, Swarnalatha Radhakrishnan, Roshan G. Ragel, Jude Angelo Ambrose, Jrg Henkel, Sri Parameswaran |
| 2013 | DATE | An extremely compact JPEG encoder for adaptive embedded systems. | Josef Schneider, Sri Parameswaran |
| 2013 | ICCAD | DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems. | Tuo Li, Muhammad Shafique, Semeen Rehman, Jude Angelo Ambrose, Jrg Henkel, Sri Parameswaran |
| 2013 | ICCD | Energy-aware synthesis of application specific MPSoCs. | Thannirmalai Somu Muthukaruppan, Haris Javaid, Tulika Mitra, Sri Parameswaran |
| 2013 | ISCAS | Latency-constrained binding of data flow graphs to energy conscious GALS-based MPSoCs. | Jude Angelo Ambrose, Isuru Nawinne, Sri Parameswaran |
| 2013 | ISCAS | Variable increment step based reconfigurable interleaver for multimode communication application. | Liang Tang, Jude Angelo Ambrose, Sri Parameswaran |
| 2013 | VLSID | A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors. | Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose, Sri Parameswaran |
| 2013 | VLSID | MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping. | Liang Tang, Jude Angelo Ambrose, Sri Parameswaran |
| 2012 | DATE | Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors. | Tuo Li, Roshan G. Ragel, Sri Parameswaran |
| 2012 | ICCAD | Fine-grained hardware/software methodology for process migration in MPSoCs. | Tuo Li, Jude Angelo Ambrose, Sri Parameswaran |
| 2012 | ISCAS | CoRaS: A multiprocessor key corruption and random round swapping for power analysis side channel attacks: A DES case study. | Jude Angelo Ambrose, Aleksandar Ignjatovic, Sri Parameswaran |
| 2012 | VLSID | A Rapid Methodology for Multi-mode Communication Circuit Generation. | Liang Tang, Jorgen Peddersen, Sri Parameswaran |
| 2011 | DAC | Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study. | Haris Javaid, Muhammad Shafique, Sri Parameswaran, Jrg Henkel |
| 2011 | ICCAD | CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. | Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran |
| 2011 | ICCAD | System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia. | Haris Javaid, Muhammad Shafique, Jrg Henkel, Sri Parameswaran |
| 2011 | TrustCom | A Hardware/Software Countermeasure and a Testing Framework for Cache Based Side Channel Attacks. | Ankita Arora, Sri Parameswaran, Roshan G. Ragel, Darshana Jayasinghe |
| 2011 | VLSID | Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. | Su Myat Min, Jorgen Peddersen, Sri Parameswaran |
| 2010 | DAC | SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. | Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran |
| 2010 | DATE | DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. | Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran |
| 2010 | DATE | Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. | Andhi Janapsatya, Aleksandar Ignjatovic, Jorgen Peddersen, Sri Parameswaran |
| 2010 | DATE | Rapid runtime estimation methods for pipelined MPSoCs. | Haris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran |
| 2010 | ICCAD | Fidelity metrics for estimation models. | Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran |
| 2010 | NCA | Improved Architectures for Range Encoding in Packet Classification System. | Xin He, Jorgen Peddersen, Sri Parameswaran |
| 2009 | ASPDAC | HitME: low power Hit MEmory buffer for embedded systems. | Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic |
| 2009 | DAC | A design flow for application specific heterogeneous pipelined multiprocessor systems. | Haris Javaid, Sri Parameswaran |
| 2009 | DATE | CUFFS: An instruction count based architectural framework for security of MPSoCs. | Krutartha Patel, Sri Parameswaran, Roshan G. Ragel |
| 2009 | FPGA | Flexible multi-mode embedded floating-point unit for field programmable gate arrays. | Yee Jern Chong, Sri Parameswaran |
| 2009 | LCN | LOP_RE: Range encoding for low power packet classification. | Xin He, Jorgen Peddersen, Sri Parameswaran |
| 2009 | VLSID | Security and Dependability of Embedded Systems: A Computer Architects' Perspective. | Jrg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Roshan G. Ragel |
| 2008 | ASPDAC | NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks. | Jeremy Chan, Sri Parameswaran |
| 2008 | DAC | Rapid application specific floating-point unit generation with bit-alignment. | Yee Jern Chong, Sri Parameswaran |
| 2008 | DAC | SHIELD: a software hardware design methodology for security and reliability of MPSoCs. | Krutartha Patel, Sri Parameswaran |
| 2008 | DATE | A Formal Approach To The Protocol Converter Problem. | Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran |
| 2008 | ICCAD | MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm. | Jude Angelo Ambrose, Sri Parameswaran, Aleksandar Ignjatovic |
| 2008 | SYNASC | Anatomy of Differential Power Analysis for AES. | Jude Angelo Ambrose, Naeill Aldon, Aleksandar Ignjatovic, Sri Parameswaran |
| 2007 | ASPDAC | CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. | Jorgen Peddersen, Sri Parameswaran |
| 2007 | DAC | RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks. | Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran |
| 2007 | DAC | Design Methodology for Pipelined Heterogeneous Multiprocessor System. | Seng Lin Shee, Sri Parameswaran |
| 2007 | DATE | Automatic application specific floating-point unit generation. | Yee Jern Chong, Sri Parameswaran |
| 2007 | DATE | Instruction trace compression for rapid instruction cache simulation. | Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jrg Henkel |
| 2007 | VLSID | Energy Driven Application SelfAdaptation. | Jorgen Peddersen, Sri Parameswaran |
| 2006 | ASPDAC | A novel instruction scratchpad memory optimization method based on concomitance metric. | Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran |
| 2006 | ASPDAC | Finding optimal L1 cache configuration for embedded systems. | Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran |
| 2006 | DAC | IMPRES: integrated monitoring for processor reliability and security. | Roshan G. Ragel, Sri Parameswaran |
| 2006 | DATE | Customization of application specific heterogeneous multi-pipeline processors. | Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran |
| 2006 | VLSID | ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective. | Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran |
| 2005 | ASPDAC | Battery-aware instruction generation for embedded processors. | Newton Cheung, Sri Parameswaran, Jrg Henkel |
| 2005 | CASES | Micro embedded monitoring for security in application specific instruction-set processors. | Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia |
| 2005 | ICCAD | NoCEE: energy macro-model extraction methodology for network on chip routers. | Jeremy Chan, Sri Parameswaran |
| 2005 | WCNC | The effect of receiver front-end non-linearity on DS-UWB systems operating in the 3 to 4 GHz band. | Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran |
| 2005 | VLSID | Rapid Embedded Hardware/Software System Generation. | Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran |
| 2004 | DATE | MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor. | Newton Cheung, Sri Parameswaran, Jrg Henkel, Jeremy Chan |
| 2004 | ICCAD | A quantitative study and estimation models for extensible instructions in embedded processors. | Newton Cheung, Sri Parameswaran, Jrg Henkel |
| 2004 | ICCAD | Hardware/software managed scratchpad memory for embedded system. | Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic |
| 2004 | VLSID | NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture. | Jeremy Chan, Sri Parameswaran |
| 2003 | ASPDAC | Multi-parametric improvements for embedded systems using code-placement and address bus coding. | Sri Parameswaran, Jrg Henkel, Haris Lekatsas |
| 2003 | DATE | Rapid Configuration and Instruction Selection for an ASIP: A Case Study. | Newton Cheung, Jrg Henkel, Sri Parameswaran |
| 2003 | ICCAD | INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors. | Newton Cheung, Sri Parameswaran, Jrg Henkel |
| 2003 | VLSID | Specification and Design of Multi-Million Gate SOCs. | Ramesh Chandra, Preeti Ranjan Panda, Jrg Henkel, Sri Parameswaran, Loganath Ramachandran |
| 2002 | VLSID | SWASAD: An ASIC Design for High Speed DNA Sequence Matching. | Tony Han, Sri Parameswaran |
| 2001 | DATE | Code placement in hardware/software co-synthesis to improve performance and reduce cost. | Sri Parameswaran |
| 2001 | ICCAD | I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency. | Sri Parameswaran, Jrg Henkel |
| 2000 | ASPDAC | Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation. | Allan Rae, Sri Parameswaran |
| 2000 | DAC | High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system. | Vince E. Boros, Aleksandar D. Rakic, Sri Parameswaran |
| 1998 | ASPDAC | Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines. | Hui Guo, Sri Parameswaran |
| 1998 | ASPDAC | HW-SW Co-Synthesis: The Present and The Future (Embedded Tutorial). | Sri Parameswaran |
| 1998 | ASPDAC | Power Reduction in Pipelines. | Sri Parameswaran, Hui Guo |
| 1997 | ASPDAC | Power consumption in CMOS combinational logic blocks at high frequencies. | Sri Parameswaran, Hui Guo |
| 1995 | ASPDAC | Reclocking for high-level synthesis. | Pradip K. Jha, Nikil D. Dutt, Sri Parameswaran |
| 1994 | VTS | Novel architectures for TSC/CD and SFS/SCD synchronous controllers. | Sayed Mohammad Kia, Sri Parameswaran |