| 2026 | VTS | Innovative Practices Session: Efficient Multi-Die Test Architecture & Repair Methods. | Tapan J. Chakraborty, Rajesh Pendurkar, Anshuman Chandra, Jennifer Dworak, Moiz Khan, Vinay Kumar Kotha |
| 2013 | ICCD | Functional Fmax test-time reduction using novel DFTs for circuit initialization. | Ujjwal Guin, Tapan J. Chakraborty, Mohammad Tehranipoor |
| 2008 | ITC | A New Language Approach for IJTAG. | Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook |
| 2008 | VLSID | A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits. | Aditya Jagirdar, Roystein Oliveira, Tapan J. Chakraborty |
| 2007 | ITC | A practical approach to comprehensive system test & debug using boundary scan based test architecture. | Tapan J. Chakraborty, Chen-Huan Chiang, Bradford G. Van Treuren |
| 2002 | ITC | A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur. | Tapan J. Chakraborty, Chen-Huan Chiang |
| 1998 | ITC | A BIST scheme for the detection of path-delay faults. | Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik |
| 1997 | ITC | Effective Path Selection for Delay Fault Testing of Sequential Circuits. | Tapan J. Chakraborty, Vishwani D. Agrawal |
| 1996 | VLSID | Design for high-speed testability of stuck-at faults. | Tapan J. Chakraborty, Vishwani D. Agrawal |
| 1995 | ITC | High-Performance Circuit Testing with Slow-Speed Testers. | Vishwani D. Agrawal, Tapan J. Chakraborty |
| 1995 | VLSID | Robust testing for stuck-at faults. | Tapan J. Chakraborty, Vishwani D. Agrawal |
| 1995 | VTS | Simulation of at-speed tests for stuck-at faults. | Tapan J. Chakraborty, Vishwani D. Agrawal |
| 1993 | DAC | Design for Testability for Path Delay faults in Sequential Circuits. | Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell |
| 1993 | VTS | Partial scan testing with single clock control. | Vishwani D. Agrawal, Tapan J. Chakraborty |
| 1992 | DAC | Delay Fault Models and Test Generation for Random Logic Sequential Circuits. | Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell |
| 1991 | DAC | Enhanced Controllability for | Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin |
| 1988 | ITC | On Behavior Fault Modeling for Combinational Digital Designs. | Tapan J. Chakraborty, Sumit Ghosh |