| 2016 | ITC | A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath. | V. R. Devanathan, Sumant Kale |
| 2015 | VLSID | New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation. | V. R. Devanathan, Lakshmanan Balasubramanian, Rubin A. Parekhji |
| 2015 | VLSID | Framework for Selective Flip-Flop Replacement for Soft Error Mitigation. | Pavan Vithal Torvi, V. R. Devanathan, V. Kamakoti |
| 2014 | VLSID | ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. | Neel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti |
| 2013 | DATE | Towards adaptive test of multi-core RF SoCs. | Rajesh Mittal, Lakshmanan Balasubramanian, Y. B. Chethan Kumar, V. R. Devanathan, Mudasir Kawoosa, Rubin A. Parekhji |
| 2011 | ITC | Techniques to improve memory interface test quality for complex SoCs. | V. R. Devanathan, Srinivas Kumar Vooka |
| 2011 | VLSID | Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test. | V. R. Devanathan, Ishaan Santhosh Shah |
| 2010 | ITC | Towards effective and compression-friendly test of memory interface logic. | V. R. Devanathan, Alan Hales, Sumant Kale, Dharmesh Sonkar |
| 2007 | DATE | Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
| 2007 | ICCAD | Methodology for low power test pattern generation using activity threshold control logic. | Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji |
| 2007 | ITC | A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
| 2007 | ITC | PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. | V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti |
| 2007 | VLSID | Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
| 2007 | VTS | Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
| 2005 | VLSID | A Framework for Distributed and Hierarchical Design-for-Test. | C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar |