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Vikram Chandrasekhar

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

16

Venues

10

Active years

2002–2020

Best venue rank

A*

Where they publish

Papers

16 indexed papers, newest first.

YearVenueTitleAuthors
2020AAAIDeep Reservoir Computing Meets 5G MIMO-OFDM Systems in Symbol Detection.Zhou Zhou, Lingjia Liu, Vikram Chandrasekhar, Jianzhong Zhang, Yang Yi
2011CISSFrom homogeneous to heterogeneous networks: A 3GPP Long Term Evolution rel 8/9 case study.Ralf M. Bendlin, Vikram Chandrasekhar, Runhua Chen, Anthony E. Ekpenyong, Eko N. Onggosanusi
2010GLOBECOMFemtocell Access Control in the TDMA/OFDMA Uplink.Ping Xia, Vikram Chandrasekhar, Jeffrey G. Andrews
2009GLOBECOMDistributed Power Control in Femtocell-Underlay Cellular Networks.Vikram Chandrasekhar, Jeffrey G. Andrews, Zukang Shen, Tarik Muharemovic, Alan Gatherer
2009GLOBECOMCoverage in Tiered Cellular Networks with Spatial Diversity.Vikram Chandrasekhar, Marios Kountouris, Jeffrey G. Andrews
2008ACSSCSpectrum allocation in two-tier networks.Vikram Chandrasekhar, Jeffrey G. Andrews
2008ICASSPOptimal power allocation for sum capacity of a slotted three-cell system.Vikram Chandrasekhar, Zukang Shen, Vijay Sundararajan
2007GLOBECOMUplink Capacity and Interference Avoidance for Two-Tier Cellular Networks.Vikram Chandrasekhar, Jeffrey G. Andrews
2007MICROA Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs.William Thies, Vikram Chandrasekhar, Saman P. Amarasinghe
2006VLSIDAn Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs.Vivek Garg, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti
2005ASPDACA novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs.Vivek Garg, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti
2005ASPDACA function generator-based reconfigurable system.Vivek Garg, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti
2005ASPDACCluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan
2005FPGAEfficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only).E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan
2005VLSIDDetecting SEU-Caused Routing Errors in SRAM-Based FPGAs.E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan
2002ISCASHandset detector architectures for DS-CDMA wireless systems.Frank Livingston, Vikram Chandrasekhar, Mani Vaya, Joseph R. Cavallaro