Vivek De

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

Venues

Active years

1996–2022

Best venue rank

Where they publish

Papers

53 indexed papers, newest first.

Year	Venue	Title	Authors
2022	DAC	Improving compute in-memory ECC reliability with successive correction.	Brian Crafton, Zishen Wan, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury
2018	DATE	Exploiting on-chip power management for side-channel security.	Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2017	ISLPED	Invited paper: Low power requirements and side-channel protection of encryption engines: Challenges and opportunities.	Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2016	ICCD	What does ultra low power requirements mean for side-channel secure cryptography?	Monodeep Kar, Arvind Singh, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2016	ISLPED	Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines.	Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2015	ICCAD	Fine-Grain Power Management in Manycore Processor and System-on-Chip (SoC) Designs.	Vivek De
2014	ASPDAC	Resiliency for many-core system on a chip.	Tanay Karnik, James W. Tschanz, Nitin Borkar, Jason Howard, Sriram R. Vangal, Vivek De, Shekhar Borkar
2013	DATE	Near-threshold voltage design in nanoscale CMOS.	Vivek De
2013	HPDC	Circuits for resilient systems.	Vivek De
2012	DATE	Design for test and reliability in ultimate CMOS.	Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep P. Kulkarni, Vivek De, Dimiter Avresky
2010	ASPDAC	Resilient design in scaled CMOS for energy efficiency.	James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep P. Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De
2010	ISLPED	Resilient microprocessor design for high performance & energy efficiency.	Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2009	DAC	Circuit techniques for dynamic variation tolerance.	Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar
2008	ICCAD	Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design.	Hamed F. Dadgour, Vivek De, Kaustav Banerjee
2007	DAC	Comparative Analysis of Conventional and Statistical Design Techniques.	Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De
2006	ISCAS	Reducing the data switching activity of serialized datastreams.	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
2006	ISCAS	Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches.	Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De
2006	ISLPED	Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.	Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De
2006	VLSID	Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design.	Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak
2005	DAC	Variations-aware low-power design with voltage scaling.	Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
2005	DAC	Variation-tolerant circuits: circuit solutions and techniques.	James W. Tschanz, Keith A. Bowman, Vivek De
2005	ICCAD	Serial-link bus: a low-power on-chip bus architecture.	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
2005	ICCAD	Total power-optimal pipelining and parallel processing under process variations in nanometer technology.	Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge
2005	ICCD	A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS.	Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De
2005	ISCAS	Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses.	Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Vivek De
2005	ISCAS	Cascode buffer for monolithic voltage conversion operating at high input supply voltages.	Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva G. Narendra
2005	ISCAS	Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power.	James W. Tschanz, Siva G. Narendra, Ali Keshavarzi, Vivek De
2005	ISLPED	Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage.	Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De
2004	DAC	Design and reliability challenges in nanometer technologies.	Shekhar Borkar, Tanay Karnik, Vivek De
2004	DAC	Design optimizations for microprocessors at low temperature.	Arman Vassighi, Ali Keshavarzi, Siva G. Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De
2004	ISLPED	Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation.	Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva G. Narendra, Tanay Karnik, Vivek De
2003	DAC	Parameter variations and impact on circuits and microarchitecture.	Shekhar Borkar, Tanay Karnik, Siva G. Narendra, James W. Tschanz, Ali Keshavarzi, Vivek De
2003	DATE	Compiler Support for Reducing Leakage Energy Consumption.	Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De
2003	ISLPED	Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation.	Stephen Tang, Siva G. Narendra, Vivek De
2002	DAC	Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.	Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar
2002	DAC	Life is CMOS: why chase the life after?	George Sery, Shekhar Borkar, Vivek De
2002	ICCAD	Sub-90nm technologies: challenges and opportunities for CAD.	Tanay Karnik, Shekhar Borkar, Vivek De
2002	ISLPED	Full-chip sub-threshold leakage power prediction model for sub-0.18 m CMOS.	Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan
2002	VTS	Challenges in Nanometric Technology Scaling: Trends and Projections.	Jaume Segura, Vivek De, Ali Keshavarzi
2001	ISLPED	Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs.	Ali Keshavarzi, Sean Ma, Siva G. Narendra, Brad Bloechel, K. Mistry, Tahir Ghani, Shekhar Borkar, Vivek De
2001	ISLPED	Scaling of stack effect and its application for leakage reduction.	Siva G. Narendra, Vivek De, Dimitri A. Antoniadis, Anantha P. Chandrakasan, Shekhar Borkar
2001	ISLPED	Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.	James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De
2000	DAC	Dynamic noise analysis in precharge-evaluate circuits.	Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De
2000	ITC	Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ.	Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, Krishnamurthy Soumyanath, Vivek De
2000	VLSID	Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs.	Liqiong Wei, Kaushik Roy, Vivek De
1999	DAC	Mixed-	Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De
1999	ISLPED	Technology and design challenges for low power and high performance.	Vivek De, Shekhar Borkar
1999	ISLPED	Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's.	Ali Keshavarzi, Siva G. Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De
1998	DAC	Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits.	Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De
1997	DAC	Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks.	Pankaj Pant, Vivek De, Abhijit Chatterjee
1996	ISLPED	Circuit techniques for low-power CMOS GSI.	Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl
1996	ISLPED	A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI).	Vivek De, James D. Meindl
1996	ISLPED	Effects of random MOSFET parameter fluctuations on total power consumption.	Xinghai Tang, Vivek De, James D. Meindl