| 2021 | VTS | Timing Critical Path Validation for Intel ATOM Cores Using Structural Test. | Wei Li, Shih-Yu Yang, Khen Wee, Ricardo Sanchez, Jay Desai, Kun-Han Tsai, Xijiang Lin |
| 2020 | ITC | Test Challenges of Intel IA Cores. | Uri Shpiro, Khen Wee, Kun-Han Tsai, Justyna Zawada, Xijiang Lin |
| 2019 | ETS | On Generating Fault Diagnosis Patterns for Designs with X Sources. | Xijiang Lin, Sudhakar M. Reddy |
| 2017 | ITC | On applying scan based structural test for designs with dual-edge triggered flip-flops. | Xijiang Lin |
| 2016 | ETS | Transistor stuck-on fault detection tests for digital CMOS circuits. | Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski |
| 2015 | ITC | On generating high quality tests based on cell functions. | Xijiang Lin, Sudhakar M. Reddy |
| 2015 | VLSID | Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. | Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski |
| 2014 | ETS | Using dynamic shift to reduce test data volume in high-compression designs. | Xijiang Lin, Mark Kassab, Janusz Rajski |
| 2010 | ITC | Low capture power at-speed test in EDT environment. | Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab |
| 2010 | ITC | Detecting and diagnosing open defects. | Dat Tran, LeRoy Winemberg, Darrell Carder, Xijiang Lin, Joe LeBritton, Bruce Swanson |
| 2010 | ITC | Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. | Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab |
| 2008 | ITC | Low Power Scan Shift and Capture in the EDT Environment. | Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer |
| 2008 | ITC | Test Generation for Interconnect Opens. | Xijiang Lin, Janusz Rajski |
| 2008 | VTS | Reducing Scan Shift Power at RTL. | Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak |
| 2007 | VLSID | Low Shift and Capture Power Scan Tests. | Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski |
| 2006 | ITC | Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. | Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski |
| 2006 | VTS | The Impacts of Untestable Defects on Transition Fault Testing. | Xijiang Lin, Janusz Rajski |
| 2006 | VTS | Scan Tests with Multiple Fault Activation Cycles for Delay Faults. | Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski |
| 2005 | ASPDAC | Propagation delay fault: a new fault model to test delay faults. | Xijiang Lin, Janusz Rajski |
| 2005 | DATE | Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. | Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press |
| 2005 | VTS | Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study. | Matthias Beck, Olivier Barondeau, Frank Poehl, Xijiang Lin, Ron Press |
| 2003 | DAC | Test generation for designs with multiple clocks. | Xijiang Lin, Rob Thompson |
| 2002 | ICCAD | Conflict driven techniques for improving deterministic test pattern generation. | Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski |
| 2002 | VTS | Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. | Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich |
| 2001 | ITC | On static test compaction and test pattern ordering for scan designs. | Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | VTS | SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. | Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | DATE | Full Scan Fault Coverage With Partial Scan. | Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | ICCAD | Techniques for improving the efficiency of sequential circuit test generation. | Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | VTS | Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. | Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin |
| 1998 | ICCD | On finding undetectable and redundant faults in synchronous sequential circuits. | Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy |
| 1998 | VLSID | MIX: A Test Generation System for Synchronous Sequential Circuits. | Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy |
| 1998 | VTS | On Removing Redundant Faults in Synchronous Sequential Circuits. | Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy |