| 2025 | ISCAS | ROFD: Event-based 5k-fps Real-Time Optical Flow Detector for Transient Radiant Expanding Flares. | Shen Zhang, Boyi Wei, Jing Jin, Yibo Zhang, Wenzhe Zheng, Yan Shen, Weixiong Jiang, Chenyang Shi, Yajun Ha |
| 2024 | ISCAS | The Optimization of Aging-aware 8T SRAM for FPGA Configuration Memory. | Yifei Li, Yuxin Zhou, Yuhao Shu, Hongyu Chen, Yajun Ha |
| 2024 | ISCAS | EarFDA: A Lightweight and Energy-Efficient Fall Detection Accelerator for Ear-Worn Devices. | Zhaodong Lv, Hao Sun, Yuhao Shu, Yajun Ha |
| 2024 | ISCAS | Machine Learning with Real-time and Small Footprint Anomaly Detection System for In-Vehicle Gateway. | Yi Wang, Yuanjin Zheng, Yajun Ha |
| 2023 | DAC | Fast FPGA Accelerator of Graph Cut Algorithm with Out-of-order Parallel Execution in Folding Grid Architecture. | Guangyao Yan, Xinzhe Liu, Hui Wang, Yajun Ha |
| 2023 | ISCAS | CSDB-eDRAM: A 16Kb Energy-Efficient 4T CSDB Gain Cell eDRAM with over 16.6s Retention Time and 49.23uW/Kb at 4.2K for Cryogenic Computing. | Yuhao Shu, Hongtu Zhang, Hao Sun, Qi Deng, Yajun Ha |
| 2023 | ISCAS | RPS-KNN: An Ultra-Fast FPGA Accelerator of Range-Projection-Structure K-Nearest-Neighbor Search for LiDAR Odometry in Smart Vehicles. | Jianzhong Xiao, Hao Sun, Qi Deng, Xinzhe Liu, Hongtu Zhang, Chengzhang He, Yuhao Shu, Yajun Ha |
| 2022 | ICCAD | WSQ-AdderNet: Efficient Weight Standardization Based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization. | Yunxiang Zhang, Biao Sun, Weixiong Jiang, Yajun Ha, Miao Hu, Wenfeng Zhao |
| 2022 | ISCAS | An Ultra Energy Efficient Streaming-based FPGA Accelerator for Lightweight Neural Network. | Shaoyi Chen, Zhiqi Zhou, Yajun Ha |
| 2021 | DAC | TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer. | Weixiong Jiang, Heng Yu, Xinzhe Liu, Hao Sun, Rui Li, Yajun Ha |
| 2021 | DAC | Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation. | Xinzhe Liu, Fupeng Chen, Raees Kizhakkumkara Muhamad, David Blinder, Dessislava Nikolova, Peter Schelkens, Francky Catthoor, Yajun Ha |
| 2021 | ISCAS | A Fault Resistant AES via Input-Output Differential Tables with DPA Awareness. | Yi Wang, Marc Stttinger, Yajun Ha |
| 2021 | ISCAS | CLIF: Cross-Layer Information Fusion for Stereo Matching and its Hardware Implementation. | Fupeng Chen, Xinzhe Liu, Heng Yu, Yajun Ha |
| 2020 | DAC | DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs. | Rui Li, Heng Yu, Weixiong Jiang, Yajun Ha |
| 2020 | ISCAS | An Accurate FPGA Online Delay Monitor Supporting All Timing Paths. | Weixiong Jiang, Rui Li, Heng Yu, Yajun Ha |
| 2020 | ISCAS | Energy-Efficient Arbitrary Precision Multi-Bit Multiplication with Bi-Serial In/Near Memory Computing. | Yuqi Wang, Jian Chen, Yu Pu, Yajun Ha |
| 2016 | FPL | ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning. | Chin Hau Hoo, Yajun Ha, Akash Kumar |
| 2016 | ISCAS | High throughput and resource efficient AES encryption/decryption for SANs. | Yi Wang, Yajun Ha |
| 2016 | PAKDD | Parallel Discord Discovery. | Tian Huang, Yongxin Zhu, Yishu Mao, Xinyang Li, Mengyun Liu, Yafei Wu, Yajun Ha, Gillian Dobbie |
| 2015 | FPL | ParaLaR: A parallel FPGA router based on Lagrangian relaxation. | Chin Hau Hoo, Akash Kumar, Yajun Ha |
| 2015 | ISCAS | AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption. | Wenfeng Zhao, Yajun Ha, Massimo Alioto |
| 2014 | DATE | Thermal-aware frequency scaling for adaptive workloads on heterogeneous MPSoCs. | Heng Yu, Rizwan Syed, Yajun Ha |
| 2013 | ASPDAC | TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs. | Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo |
| 2013 | FCCM | High Speed Video Processing Using Fine-Grained Processing on FPGA Platform. | Zhi Ping Ang, Akash Kumar, Yajun Ha |
| 2013 | FPL | A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm. | Chin Hau Hoo, Yajun Ha, Akash Kumar |
| 2013 | FPL | Criticality-based routing for FPGAS with reverse body bias switch box architectures. | Wei Ting Loke, Wenfeng Zhao, Yajun Ha |
| 2013 | FPL | FPGA based Rekeying for cryptographic key management in Storage Area Network. | Yi Wang, Yajun Ha |
| 2013 | ISCAS | An area-efficient shuffling scheme for AES implementation on FPGA. | Yi Wang, Yajun Ha |
| 2013 | ISLPED | Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology. | Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, Anastacia B. Alvarez |
| 2012 | FPGA | Power-aware FPGA technology mapping for programmable-VT architectures (abstract only). | Wei Ting Loke, Yajun Ha |
| 2011 | ISCAS | A Hilbert curve-based delay fault characterization method for FPGAs. | Wenjuan Zhang, Yajun Ha |
| 2010 | DAC | Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems. | Heng Yu, Bharadwaj Veeravalli, Yajun Ha |
| 2010 | ISCAS | Communication-aware application mapping and scheduling for NoC-based MPSoCs. | Heng Yu, Yajun Ha, Bharadwaj Veeravalli |
| 2010 | RSP | Performance-cost analyses software for H.264 Forward/Inverse Integer Transform. | Trang T. T. Do, Thinh M. Le, Binh P. Nguyen, Yajun Ha |
| 2009 | ASPDAC | An optimized design for serial-parallel finite field multiplication over | Pramod Kumar Meher, Yajun Ha, Chiou-Yng Lee |
| 2009 | FPL | sFPGA2 - A scalable GALS FPGA architecture and design methodology. | Rizwan Syed, Xiaolei Chen, Yajun Ha, Bharadwaj Veeravalli |
| 2008 | ASPDAC | Statistical noise margin estimation for sub-threshold combinational circuits. | Yu Pu, Jos de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha |
| 2008 | ASPDAC | Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systems. | Heng Yu, Bharadwaj Veeravalli, Yajun Ha |
| 2008 | FCCM | An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects. | Hanyu Liu, Xiaolei Chen, Yajun Ha |
| 2008 | FPL | sFPGA - A scalable switch based FPGA architecture and design methodology. | Shakith Fernando, Xiaolei Chen, Yajun Ha |
| 2008 | FPL | An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects. | Hanyu Liu, Xiaolei Chen, Yajun Ha |
| 2008 | FPL | Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA. | Haiting Tian, Shakith Fernando, Hock Wei Soon, Yajun Ha, Nanguang Chen |
| 2008 | FPL | A low overhead fault tolerant FPGA with new connection box. | Fujie Wong, Yajun Ha |
| 2007 | DAC | A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices. | Akash Kumar, Bart Mesman, Henk Corporaal, Bart D. Theelen, Yajun Ha |
| 2007 | FPL | Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA. | Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal |
| 2007 | FPL | Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools. | Chee Sing Lee, Wei Ting Loke, Wenjuan Zhang, Yajun Ha |
| 2007 | ISLPED | V | Yu Pu, Jos de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha |
| 2006 | ASPDAC | An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model. | Yu Pu, Yajun Ha |
| 2006 | DSD | Global Analysis of Resource Arbitration for MPSoC. | Akash Kumar, Bart Mesman, Henk Corporaal, Jef L. van Meerbergen, Yajun Ha |
| 2005 | FCCM | Design of Networked Reconfigurable Encryption Engine. | Shakith Fernando, Yajun Ha |
| 2002 | FPL | Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications. | Yajun Ha, Radovan Hipik, Serge Vernalde, Diederik Verkest, Marc Engels, Rudy Lauwereins, Hugo De Man |
| 2001 | ASPDAC | Virtual Java/FPGA interface for networked reconfiguration. | Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde, Marc Engels, Rudy Lauwereins, Hugo De Man |
| 2001 | FCCM | A SW/HW Interface API for Java/FPGA Co-Designed Applets. | Yajun Ha, Patrick Schaumont, Serge Vernalde, Marc Engels, Rudy Lauwereins, Hugo De Man |
| 2001 | FPL | Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. | Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man |
| 2000 | PDPTA | Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. | Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Hugo De Man |
| 2000 | RSP | A Hardware Virtual Machine for the Networked Reconfiguration. | Yajun Ha, Patrick Schaumont, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man |