| 2026 | ETS | Radiation Hardened and Self-Recoverable Latch Design for Quad-Node Upset Mitigation. | Evangelos Paparsenos, Yiorgos Tsiatouhas |
| 2025 | DATE | CAS-PUF: Current-Mode Array-Type Strong PUF for Secure Computing in Area Constrained SoCs. | Dimosthenis Georgoulas, Yiorgos Tsiatouhas, Vasileios Tenentes |
| 2024 | DATE | Testing Algorithms for Hard to Detect Thermal Crosstalk Induced Write Disturb Faults in Phase Change Memories. | Spyridon Spyridonos, Yiorgos Tsiatouhas |
| 2023 | ETS | SiCBit-PUF: Strong in-Cache Bitflip PUF Computation for Trusted SoCs. | Athanasios Xynos, Vasileios Tenentes, Yiorgos Tsiatouhas |
| 2020 | ETS | Monitoring of BTI and HCI Aging in SRAM Decoders. | Helen-Maria Dounavi, Yiorgos Tsiatouhas |
| 2018 | IOLTS | Periodic Aging Monitoring in SRAM Sense Amplifiers. | Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas |
| 2017 | ETS | Periodic Bias-Temperature Instability monitoring in SRAM cells. | Yiorgos Tsiatouhas |
| 2017 | IOLTS | Variation tolerant BTI monitoring in SRAM cells. | Yiorgos Sfikas, Yiorgos Tsiatouhas |
| 2015 | DATE | A method for the estimation of defect detection probability of analog/RF defect-oriented tests. | John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas |
| 2015 | DATE | Fast deployment of alternate analog test using Bayesian model fusion. | John Liaperdos, Haralampos-G. D. Stratigopoulos, Louay Abdallah, Yiorgos Tsiatouhas, Angela Arapoyanni, Xin Li |
| 2015 | ETS | On resistive open defect detection in DRAMs: The charge accumulation effect. | Yiorgos Sfikas, Yiorgos Tsiatouhas, Mottaqiallah Taouil, Said Hamdioui |
| 2015 | IOLTS | Soft error immune latch under SEU related double-node charge collection. | Katerina Katsarou, Yiorgos Tsiatouhas |
| 2015 | ISCAS | On the reuse of existing error tolerance circuitry for low power scan testing. | Anthi Anastasiou, Yiorgos Tsiatouhas, Angela Arapoyanni |
| 2014 | ETS | Power efficient scan testing by exploiting existing error tolerance circuitry in a design. | Anthi Anastasiou, Yiorgos Tsiatouhas |
| 2014 | IOLTS | Double node charge sharing SEU tolerant latch design. | Katerina Katsarou, Yiorgos Tsiatouhas |
| 2013 | IOLTS | NBTI aging tolerance in pipeline based designs NBTI. | Katerina Katsarou, Yiorgos Tsiatouhas, Angela Arapoyanni |
| 2012 | DDECS | Low power scan by partitioning and scan hold. | Efi Arvaniti, Yiorgos Tsiatouhas |
| 2012 | ETS | Cost and power efficient timing error tolerance in flip-flop based microprocessor cores. | Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni |
| 2011 | ETS | Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches. | Zhaobo Zhang, Xrysovalantis Kavousianos, Yan Luo, Yiorgos Tsiatouhas, Krishnendu Chakrabarty |
| 2011 | IOLTS | A BIST scheme for testing and repair of multi-mode power switches. | Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty |
| 2011 | VLSID | A Robust and Reconfigurable Multi-mode Power Gating Architecture. | Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas |
| 2010 | DDECS | A Build-In Self-Test technique for RF Mixers. | Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas |
| 2010 | IOLTS | Timing error tolerance in nanometer ICs. | Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni |
| 2009 | DDECS | Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing. | Yiorgos Sfikas, Yiorgos Tsiatouhas |