Yoshinobu Higami
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
17
Venues
9
Active years
1994–2018
Best venue rank
National
Where they publish
Papers
17 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | ETS | Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262. | Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima |
| 2017 | ACIIDS | Comparative Evaluation of Bluetooth and Wi-Fi Direct for Tablet-Oriented Educational Applications. | Keiichi Endo, Ayame Onoyama, Dai Okano, Yoshinobu Higami, Shin-ya Kobayashi |
| 2016 | ACIIDS | Design and Implementation of Data Synchronization and Offline Capabilities in Native Mobile Apps. | Kamoliddin Mavlonov, Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi |
| 2012 | PRDC | Diagnosis for Bridging Faults on Clock Lines. | Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja |
| 2011 | ASPDAC | Fault simulation and test generation for clock delay faults. | Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja |
| 2011 | ETS | Enhancement of Clock Delay Faults Testing. | Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja |
| 2009 | ITC | Diagnostic test generation for transition faults using a stuck-at ATPG tool. | Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo, Yuzo Takamatsu |
| 2009 | VLSID | A Novel Approach for Improving the Quality of Open Fault Diagnosis. | Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume |
| 2009 | VLSID | Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. | Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu |
| 2007 | VLSID | Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu |
| 2006 | ASPDAC | Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu |
| 2005 | ISCAS | On the fault diagnosis in the presence of unknown fault models using pass/fail information. | T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu |
| 2003 | ICCD | A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. | Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz |
| 2000 | ASPDAC | Fault models and test generation for IDDQ testing: embedded tutorial. | Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita |
| 1999 | VLSID | Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. | Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita |
| 1997 | DATE | Design of partially parallel scan chain. | Yoshinobu Higami, Kozo Kinoshita |
| 1994 | ITC | Reduced Scan Shift: A New Testing Method for Sequential Circuit. | Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita |