| 2009 | DDECS | An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. | Florence Azas, Yves Bertrand, Michel Renovell |
| 2008 | IOLTS | On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring. | Florence Azas, Laurent Larguier, Yves Bertrand, Michel Renovell |
| 2003 | ITC | A New Methodology For ADC Test Flow Optimization. | Serge Bernard, Mariane Comte, Florence Azas, Yves Bertrand, Michel Renovell |
| 2002 | DATE | On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems. | Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet |
| 2002 | ETS | A high accuracy triangle-wave signal generator for on-chip ADC testing. | Serge Bernard, Florence Azas, Yves Bertrand, Michel Renovell |
| 2002 | ETS | Modeling gate oxide short defects in CMOS minimum transistors. | Michel Renovell, Jean Marc Gallire, Florence Azas, Yves Bertrand |
| 2002 | VTS | Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems. | Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet |
| 2001 | DATE | Implementation of a linear histogram BIST for ADCs. | Florence Azas, Serge Bernard, Yves Bertrand, Michel Renovell |
| 2001 | ITC | Boolean and current detection of MOS transistor with gate oxide short. | Michel Renovell, Jean Marc Gallire, Florence Azas, Serge Bernard, Yves Bertrand |
| 2001 | VTS | A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. | Florence Azas, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell |
| 2001 | WSCG | N-Dimensional Gregory-Bezier for N-Dimensional Cellular Complexes. | Sylvain Thery, Dominique Bechmann, Yves Bertrand |
| 2000 | DATE | Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. | rika F. Cota, Michel Renovell, Florence Azas, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski |
| 2000 | VTS | Hardware Resource Minimization for Histogram-Based ADC BIST. | Michel Renovell, Florence Azas, Serge Bernard, Yves Bertrand |
| 1999 | DATE | Design, Characterization & Modelling of a CMOS Magnetic Field Sensor. | Laurent Latorre, Yves Bertrand, P. Hazard, Francis Pressecq, Pascal Nouet |
| 1999 | ETS | Functional and structural testing of switched-current circuits. | Michel Renovell, Florence Azas, J.-C. Bodin, Yves Bertrand |
| 1999 | ITC | Optimal conditions for Boolean and current detection of floating gate faults. | Michel Renovell, Andr Ivanov, Yves Bertrand, Florence Azas, Sumbal Rafiq |
| 1998 | DATE | Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. | Michel Renovell, Florence Azas, Yves Bertrand |
| 1998 | VTS | Design-For-Testability for Switched-Current Circuits. | Florence Azas, Michel Renovell, Yves Bertrand, J.-C. Bodin |
| 1997 | DATE | MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits. | A. Dargelas, C. Gauthron, Yves Bertrand |
| 1997 | DATE | On-chip analog output response compaction. | Michel Renovell, Florence Azas, Yves Bertrand |
| 1997 | ITC | Test Strategy Sensitivity to Defect Parameters. | Michel Renovell, Yves Bertrand |
| 1996 | EDCC | The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault. | Michel Renovell, P. Huc, Yves Bertrand |
| 1996 | VTS | The multi-configuration: A DFT technique for analog circuits. | Michel Renovell, Florence Azas, Yves Bertrand |
| 1996 | VTS | Bridging fault coverage improvement by power supply control. | Michel Renovell, P. Huc, Yves Bertrand |
| 1995 | VTS | The concept of resistance interval: a new parametric model for realistic resistive bridging fault. | Michel Renovell, P. Huc, Yves Bertrand |
| 1994 | EDCC | The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds. | Michel Renovell, P. Huc, Yves Bertrand |
| 1994 | VTS | CMOS bridging fault modeling. | Michel Renovell, P. Huc, Yves Bertrand |
| 1993 | ITC | Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. | Yves Bertrand, Frdric Bancel, Michel Renovell |
| 1993 | VLSID | A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. | Yves Bertrand, Frdric Bancel, Michel Renovell |
| 1992 | VLSID | A Low Overhead and High Coverage BIST Scheme for Dynamic CMOS PLAs. | Michel Renovell, M. Ildevert, Yves Bertrand |