| 2025 | DDECS | Domain-Specific Design Abstraction with Emphasis on Neural Networks. | Maryam Rajabalipanah, Zahra Hojati, Zahra Jahanpeima, Zainalabedin Navabi |
| 2025 | ETS | An Integrated Framework for Aging Analysis Based on an Age-Aware Cell Library. | Amirmahdi Joudi, Negin Safari, Fatemeh Mohammadzadeh, Katayoon Basharkhah, Fatemeh Sheikhshoaei, Zainalabedin Navabi |
| 2023 | DDECS | A Low-Cost Combinational Approximate Multiplier. | Zahra Hojati, Zainalabedin Navabi |
| 2023 | DDECS | A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators. | Nooshin Nosrati, Zainalabedin Navabi |
| 2023 | ETS | Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction. | Katayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad-Javad Zare, Zainalabedin Navabi |
| 2022 | ETS | Concurrent Error Detection for LSTM Accelerators. | Nooshin Nosrati, Seyedeh Maryam Ghasemi, Mahboobe Sadeghipour Roodsari, Zainalabedin Navabi |
| 2022 | IOLTS | MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors. | Nooshin Nosrati, Maksim Jenihhin, Zainalabedin Navabi |
| 2021 | ETS | Online Testing of a Row-Stationary Convolution Accelerator. | Mohammad Rasoul Roshanshah, Katayoon Basharkhah, Zainalabedin Navabi |
| 2021 | IOLTS | Integrating an Interconnect BIST with Crosstalk Avoidance Hardware. | Mahsa Akhsham, Zainalabedin Navabi |
| 2020 | DDECS | DiBA: n-Dimensional Bitslice Architecture for LSTM Implementation. | Mahboobe Sadeghipour Roodsari, Mohamad Ali Saber, Zainalabedin Navabi |
| 2020 | DDECS | Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations. | Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Zainalabedin Navabi |
| 2020 | ETS | Built-In Predictors for Dynamic Crosstalk Avoidance. | Rezgar Sadeghi, Zainalabedin Navabi |
| 2020 | VTS | ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links. | Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Zainalabedin Navabi |
| 2019 | ETS | Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme. | Mahsa Akhsham, Atefesadat Seyedolhosseini, Zainalabedin Navabi |
| 2019 | ETS | Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling. | Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi |
| 2018 | IOLTS | Near-Optimal Node Selection Procedure for Aging Monitor Placement. | Somayeh Sadeghi Kohan, Arash Vafaei, Zainalabedin Navabi |
| 2017 | DATE | TruncApp: A truncation-based approximate divider for energy efficient DSP applications. | Shaghayegh Vahdat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Zainalabedin Navabi |
| 2017 | ETS | Online Profiling for cluster-specific variable rate refreshing in high-density DRAM systems. | Rasool Sharifi, Zainalabedin Navabi |
| 2015 | DATE | Power-aware online testing of manycore systems in the dark silicon era. | Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Mohammad Fattah, Pasi Liljeberg, Juha Plosila, Zainalabedin Navabi, Hannu Tenhunen |
| 2015 | VTS | Signature oriented model pruning to facilitate multi-threaded processors debugging. | Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi |
| 2014 | ETS | Automatic correction of certain design errors using mutation technique. | Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi |
| 2014 | ETS | Homogeneous many-core processor system test distribution and execution mechanism. | Arezoo Kamran, Zainalabedin Navabi |
| 2014 | ETS | Improving polynomial datapath debugging with HEDs. | Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi |
| 2014 | ETS | An off-line MDSI interconnect BIST incorporated in BS 1149.1. | Marzieh Mohammadi, Somayeh Sadeghi Kohan, Nasser Masoumi, Zainalabedin Navabi |
| 2014 | VLSID | Configurable Systolic Matrix Multiplication. | Parastoo Kamranfar, Ali Shahabi, Ghazaleh Vazhbakht, Zainalabedin Navabi |
| 2012 | DDECS | Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST. | M. H. Haghbayan, Saeed Safari, Zainalabedin Navabi |
| 2012 | DDECS | Effective RT-level software-based self-testing of embedded processor cores. | Parisa Kabiri, Zainalabedin Navabi |
| 2012 | DSD | Soft Error Analysis on Communication Channels in On-Chip Communication Networks. | Mohammadreza Najafi, Saeed Safari, Zainalabedin Navabi |
| 2012 | ITC | BS 1149.1 extensions for an online interconnect fault detection and recovery. | Somayeh Sadeghi Kohan, Majid Namaki-Shoushtari, Fatemeh Javaheri, Zainalabedin Navabi |
| 2012 | MEMOCODE | Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2 | Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi, Masahiro Fujita |
| 2010 | ETS | A reconfigurable online BIST for combinational hardware using digital neural networks. | S. Behdad Hosseini, Ali Shahabi, Hasan Sohofi, Zainalabedin Navabi |
| 2010 | IOLTS | A partitioning approach to improve reconfigurable neuron-inspired online BIST. | Ali Shahabi, S. Behdad Hosseini, Hasan Sohofi, Zainalabedin Navabi |
| 2010 | ITC | Using context based methods for test data compression. | Sara Karamati, Zainalabedin Navabi |
| 2008 | DATE | BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs. | Pejman Lotfi-Kamran, Masoud Daneshtalab, Caro Lucas, Zainalabedin Navabi |
| 2008 | IOLTS | A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing. | Naghmeh Karimi, Soheil Aminzadeh, Saeed Safari, Zainalabedin Navabi |
| 2008 | IOLTS | Reliability in Application Specific Mesh-Based NoC Architectures. | Fatemeh Refan, Homa Alemzadeh, Saeed Safari, Paolo Prinetto, Zainalabedin Navabi |
| 2008 | ITC | NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structure. | Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Zainalabedin Navabi |
| 2008 | ITC | "Plug & Test" at System Level via Testable TLM Primitives. | Homa Alemzadeh, Stefano Di Carlo, Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi |
| 2008 | VLSID | Enhanced TED: A New Data Structure for RTL Verification. | Pejman Lotfi-Kamran, Mehran Massoumi, Mohammad Mirzaei, Zainalabedin Navabi |
| 2008 | VLSID | Stall Power Reduction in Pipelined Architecture Processors. | Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, Zainalabedin Navabi |
| 2008 | VLSID | An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations. | Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi |
| 2007 | DATE | Using the inter- and intra-switch regularity in NoC switch testing. | Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi |
| 2007 | DDECS | A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. | Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi |
| 2007 | DSD | On-Chip Verification of NoCs Using Assertion Processors. | Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi |
| 2007 | FDL | APDL: A Processor Description Language For Design Space Exploration of Embedded Processors. | Nima Honarmand, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi |
| 2007 | FDL | A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library. | Parisa Razaghi, Shahrzad Mirkhani, Zainalabedin Navabi |
| 2007 | IOLTS | An Analytical Model for Reliability Evaluation of NoC Architectures. | Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi |
| 2007 | IOLTS | Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. | Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale |
| 2007 | ISCAS | A New Approach for Design and Verification of Transaction Level Models. | Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi |
| 2007 | ISCAS | Programmable Routing Tables for Degradable Torus-Based Networks on Chips. | Ali Shahabi, Nima Honarmand, Zainalabedin Navabi |
| 2007 | VTS | High Level Synthesis of Degradable ASICs Using Virtual Binding. | Nima Honarmand, Ali Shahabi, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi |
| 2007 | VTS | A UML Based System Level Failure Rate Assessment Technique for SoC Designs. | Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi |
| 2006 | DATE | A concurrent testing method for NoC switches. | Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi |
| 2006 | ISCAS | DCim++: a C++ library for object oriented hardware design and distributed simulation. | Hadi Esmaeilzadeh, A. Moghimi, Eiman Ebrahimi, Caro Lucas, Zainalabedin Navabi, A. M. Fakhraie |
| 2006 | ISCAS | Low-power and low-latency cluster topology for local traffic NoCs. | Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi |
| 2005 | ASPDAC | TED+: a data structure for microprocessor verification. | Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi |
| 2005 | DAC | Sign bit reduction encoding for low power applications. | Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi |
| 2005 | DATE | Simultaneous Reduction of Dynamic and Static Power in Scan Structures. | Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi |
| 2005 | FDL | Combination of Assertion and HSAT Methods For Automated Test Vectors Generation. | Mostafa Naderi, Zainalabedin Navabi |
| 2005 | ISCAS | A low-power scan-path architecture. | Mohammad Alisafaee, Safar Hatami, Ehsan Atoofian, Zainalabedin Navabi, Ali Afzali-Kusha |
| 2005 | ISCAS | Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams. | Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi |
| 2005 | VLSID | An Effective VHDL-AMS Simulation Algorithm with Event Partitioning. | Hamid Reza Ghasemi, Zainalabedin Navabi |
| 2003 | PDPTA | Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching. | Morteza Fayyazi, David R. Kaeli, Zainalabedin Navabi |
| 2001 | DATE | Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation. | Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi |
| 2001 | ISCAS | An efficient BIST method for testing of embedded SRAMs. | Mohammad H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie |
| 1979 | DAC | Efficient simulation of AHPL. | Zainalabedin Navabi, Fredrick J. Hill |