| 2006 | Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. | Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula |
| 2006 | Discovering the input assumptions in specification refinement coverage. | Prasenjit Basu, Sayantan Das, Pallab Dasgupta, Partha Pratim Chakrabarti |
| 2006 | Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. | Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy |
| 2006 | Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. | Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava |
| 2006 | PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt |
| 2006 | Refinement strategies for verification methods based on datapath abstraction. | Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah |
| 2006 | Word level functional coverage computation. | Bijan Alizadeh |
| 2006 | Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA). | Vineet Agarwal, Janet Meiling Wang |
| 2006 | Analysis of scratch-pad and data-cache performance using statistical methods. | Javed Absar, Francky Catthoor |
| 2006 | Parameterized block-based non-gaussian statistical gate timing analysis. | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
| 2005 | Analysis of buffered hybrid structured clock networks. | Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan |
| 2005 | An integrated performance and power model for superscalar processor designs. | Yongxin Zhu, Weng-Fai Wong, Stefan Andrei |
| 2005 | Efficient transient simulation for transistor-level analysis. | Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh |
| 2005 | An efficient dynamic task scheduling algorithm for battery powered DVS systems. | Jianli Zhuo, Chaitali Chakrabarti |
| 2005 | Constructing zero-deficiency parallel prefix adder of minimum depth. | Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham |
| 2005 | Integrated algorithmic logical and physical design of integer multiplier. | Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng |
| 2005 | Deriving a new efficient algorithm for min-period retiming. | Hai Zhou |
| 2005 | ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress. | Rouying Zhan, Haolu Xie, Haigang Feng, Albert Wang |
| 2005 | Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up. | Yong Zhan, Sachin S. Sapatnekar |
| 2005 | Design and implementation of an SDH high-speed switch. | Dehui Zhang, Quan Liang Zhao, Jun Gang Han |
| 2005 | Buffering global interconnects in structured ASIC design. | Tianpei Zhang, Sachin S. Sapatnekar |
| 2005 | On combining iteration space tiling with data space tiling for scratch-pad memory systems. | Chunhui Zhang, Fadi J. Kurdahi |
| 2005 | A new register file access architecture for software pipelining in VLIW processors. | Yanjun Zhang, Hu He, Yihe Sun |
| 2005 | Block based statistical timing analysis with extended canonical timing model. | Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen |
| 2005 | Wave-pipelined on-chip global interconnect. | Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen |