| 2005 | Detecting support-reducing bound sets using two-cofactor symmetries. | Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch |
| 2005 | A 2.4-GHz linear-tuning CMOS LC voltage-controlled oscillator. | Hong Zhang, Guican Chen, Ning Li |
| 2005 | Architecture and performance comparison of a statistic-based lottery arbiter for shared bus on chip. | Yan Zhang |
| 2005 | A domain specific reconfigurable Viterbi fabric for system-on-chip applications. | Cheng Zhan, Tughrul Arslan, Sami Khawam, Iain Lindsay |
| 2005 | IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems. | Nacer-Eddine Zergainoh, Katalin Popovici, Ahmed Amine Jerraya, Pascal Urard |
| 2005 | A novel wavelet method for noise analysis of nonlinear circuits. | Xuan Zeng, Bang Liu, Jun Tao, Charles C. Chiang, Dian Zhou |
| 2005 | A two-stage genetic algorithm method for optimization the Sigma-Delta modulators. | Ali Zahabi, Omid Shoaei, Yarallah Koolivand, Parviz Jabedar Maralani |
| 2005 | Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practice. | Yinlei Yu, Sharad Malik |
| 2005 | A wideband hierarchical circuit reduction for massively coupled interconnects. | Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan |
| 2005 | FSM re-engineering and its application in low power state encoding. | Lin Yuan, Gang Qu, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli |
| 2005 | LFF algorithm for heterogeneous FPGA floorplanning. | Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu |
| 2005 | Low-power techniques for network security processors. | Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu |
| 2005 | Single-track asynchronous pipeline controller design. | Yong Xiao, Runde Zhou |
| 2005 | Automatic synthesis and scheduling of multirate DSP algorithms. | Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousias, Tughrul Arslan |
| 2005 | Implication of assertion graphs in GSTE. | Guowu Yang, Jin Yang, William N. N. Hung, Xiaoyu Song |
| 2005 | Low-leakage robust SRAM cell design for sub-100nm technologies. | Shengqi Yang, Wayne H. Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie |
| 2005 | An FPGA implementation of low-density parity-check code decoder with multi-rate capability. | Lei Yang, Manyuan Shen, Hui Liu, Chuanjin Richard Shi |
| 2005 | Fast synthesis of exact minimal reversible circuits using group theory. | Guowu Yang, Xiaoyu Song, William N. N. Hung, Marek A. Perkowski |
| 2005 | Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. | Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Georges G. E. Gielen |
| 2005 | Tightly integrate dynamic verification with formal verification: a GSTE based approach. | Jin Yang, Avi Puder |
| 2005 | On multiple-voltage high-level synthesis using algorithmic transformations. | Hsueh-Chih Yang, Lan-Rong Dung |
| 2005 | A new method for model based frugal OPC. | Xiaolang Yan, Ye Chen, Zheng Shi, Yue Ma |
| 2005 | CMP aware shuttle mask floorplanning. | Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong |
| 2005 | XTW, a parallel and distributed logic simulator. | Qing Xu, Carl Tropper |
| 2005 | Redundant-via enhanced maze routing for yield improvement. | Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong |