| 2001 | A single-inductor dual-output integrated DC/DC boost converter for variable voltage scheduling. | Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok |
| 2001 | VLSI floorplanning with boundary constraints based on corner block list. | Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2001 | Optimized address assignment for DSPs with SIMD memory accesses. | Markus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel |
| 2001 | A mixed-signal simulator for VHDL-AMS. | Liyi Xiao, Bin Li, Yizheng Ye, Guoyong Huang, JinJun Guo, Peng Zhang |
| 2001 | Realization of semiconductor device synthesis with the parallel genetic algorithm. | Zhao Li, Xiao-Feng Xie, Wenjun Zhang, Zhilian Yang |
| 2001 | An efficient design-for-verification technique for HDLs. | Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou |
| 2001 | Integrated power supply planning and floorplanning. | I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong |
| 2001 | A construction of minimal delay Steiner tree using two-pole delay model. | LiYi Lin, Yi-Yu Liu, TingTing Hwang |
| 2001 | Low power optimization technique for BDD mapped circuits. | Per Lindgren, Mikael Kerttu, Mitchell A. Thornton, Rolf Drechsler |
| 2001 | Design and implementation of JPEG encoder IP core. | Chung-Jr Lian, Liang-Gee Chen, Hao-Chieh Chang, Yung-Chi Chang |
| 2001 | Optimal spacing and capacitance padding for general clock structures. | Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen |
| 2001 | Imprecise data computation for high performance asynchronous processors. | Jeong-Gun Lee, Euiseok Kim, Dong-Ik Lee |
| 2001 | Memory-efficient interconnect optimization. | Minghorng Lai, D. F. Wong |
| 2001 | Module placement with boundary constraints using the sequence-pair representation. | Jianbang Lai, Ming-Shiun Lin, Ting-Chi Wang, Li-C. Wang |
| 2001 | Formal verification of pulse-mode asynchronous circuits. | Xiaohua Kong, Radu Negulescu |
| 2001 | A vector-pipeline DSP for low-rate videophones. | Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera |
| 2001 | Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. | Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai |
| 2001 | A new techology mapping for CPLD under the time constraint. | Jae-Jin Kim, Hi-Seok Kim, Chi-Ho Lin |
| 2001 | An 8-b nRERL microprocessor for ultra-low-energy applications. | Seokkee Kim, Jun-Ho Kwon, Soo-Ik Chae |
| 2001 | Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders. | Youngtae Kim, Taewhan Kim |
| 2001 | The tangram framework (embedded tutorial): asynchronous circuits for low power. | Joep L. W. Kessels, Ad M. G. Peeters |
| 2001 | A prototype chip of multicontext FPGA with DRAM for virtual hardware. | Daisuke Kawakami, Yuichiro Shibata, Hideharu Amano |
| 2001 | An RTL design-space exploration method for high-level applications. | Peng-Cheng Kao, Chih-Kuang Hsieh, Allen C.-H. Wu |
| 2001 | A C-based synthesis system, Bach, and its application (invited talk). | Takashi Kambe, Akihisa Yamada, Koichi Nishida, Kazuhisa Okada, Mitsuhisa Ohnishi, Andrew Kay, Paul Boca, Vince Zammit, Toshio Nomura |
| 2001 | New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout. | Andrew B. Kahng, Shailesh Vaya, Alexander Zelikovsky |