| 2001 | Flexible processor based on full-adder/ d-flip-flop merged module. | Satoshi Sakaidani, Naoto Miyamoto, Tadahiro Ohmi |
| 2001 | A formal approach to component based development of synchronous programs. | Partha S. Roop, Arcot Sowmya, S. Ramesh |
| 2001 | Finding an optimal functional decomposition for LUT-based FPGA synthesis. | Jian Qiao, Makoto Ikeda, Kunihiro Asada |
| 2001 | Power optimization and management in embedded systems. | Massoud Pedram |
| 2001 | A dataflow specification for system level synthesis of 3D graphics applications. | Chanik Park, Sungchan Kim, Soonhoi Ha |
| 2001 | Single chip 3D rendering engine integrating embedded DRAM frame buffer and Hierarchical Octet Tree (HOT) array processor with bandwidth amplification. | Yong-Ha Park, Seon-Ho Han, Hoi-Jun Yoo |
| 2001 | Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. | Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori |
| 2001 | Realtime wavelet video coder based on reduced memory accessing. | Roberto Yusi Omaki, Yu Dong, Morgan Hirosuke Miki, Makoto Furuie, Daisuke Taki, Masaya Tarui, Gen Fujita, Takao Onoye, Isao Shirakawa |
| 2001 | Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communication. | Takanori Okuma, Koji Hashimoto, Kazuaki J. Murakami |
| 2001 | A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability. | Satoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara |
| 2001 | A parallel vector quantization processor featuring an efficient search algorithm for real-time motion picture compression. | Toshiyuki Nozawa, Makoto Imai, Masanori Fujibayashi, Tadahiro Ohmi |
| 2001 | A smart position sensor for 3-D measurement. | Tomohiro Nezuka, Masashi Hoshino, Makoto Ikeda, Kunihiro Asada |
| 2001 | Modeling and forecasting of manufacturing variations (embedded tutorial). | Sani R. Nassif |
| 2001 | Speech recognition chip for monosyllables. | Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe |
| 2001 | A real-time 64-monosyllable recognition LSI with learning mechanism. | Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe |
| 2001 | Test circuits for substrate noise evaluation in CMOS digital ICs. | Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata |
| 2001 | Timed circuits: a new paradigm for high-speed design. | Chris J. Myers, Wendy Belluomini, Kip Kallpack, Eric Peskin, Hao Zheng |
| 2001 | A novel network node architecture for high performance and function flexibility. | Takahiro Murooka, Atsushi Takahara, Toshiaki Miyazaki |
| 2001 | Efficient global fanout optimization algorithms. | Rajeev Murgai |
| 2001 | Reducing cache engery through dual voltage supply. | Vasily G. Moshnyaga |
| 2001 | Correlation method of circuit-performance and technology fluctuations for improved design reliability. | D. Miyawaki, Shizunori Matsumoto, Hans Jrgen Mattausch, S. Ooshiro, Masami Suetake, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama |
| 2001 | Area/delay estimation for digital signal processor cores. | Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2001 | A dynamically reconfigurable hardware-based cipher chip. | Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa |
| 2001 | A new partitioning scheme for improvement of image computation. | Christoph Meinel, Christian Stangier |
| 2001 | High-level specification and efficient implementation of pipelined circuits. | Maria-Cristina V. Marinescu, Martin C. Rinard |