| 2001 | A dynamically phase adjusting PLL with a variable delay. | Takeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera |
| 2001 | A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance. | Zhaozhi Yang, Zeyi Wang, Shuzhou Fang |
| 2001 | Low-power high-level synthesis using latches. | Woo-Seung Yang, In-Cheol Park, Chong-Min Kyung |
| 2001 | Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks. | Kenneth Yan |
| 2001 | A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. | Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada |
| 2001 | A high-speed FIR digital filter with CSD coefficients implemented on FPGA. | Mitsuru Yamada, Akinori Nishihara |
| 2001 | RSA cryptosystem design based on the Chinese remainder theorem. | Chung-Hsien Wu, Jin-Hua Hong, Cheng-Wen Wu |
| 2001 | Power minization in LUT-based FPGA technology mapping. | Zhi-Hong Wang, En-Cheng Liu, Jianbang Lai, Ting-Chi Wang |
| 2001 | Design rewiring based on diagnosis techniques. | Andreas G. Veneris, Magdy S. Abadir, Ivor Ting |
| 2001 | A statistical static timing analysis considering correlations between delays. | Shuji Tsukiyama, Masakazu Tanaka, Masahiro Fukui |
| 2001 | Processor-programmable memory BIST for bus-connected embedded memories. | Ching-Hong Tsai, Cheng-Wen Wu |
| 2001 | A pipelined ADC macro design for multiple applications. | Kuniyuki Tani, Norihiro Nikai, Atsushi Wada, Tetsuro Sawai |
| 2001 | FAST-SP: a fast algorithm for block placement based on sequence pair. | Xiaoping Tang, D. F. Wong |
| 2001 | Improved alternative wiring scheme applying dominator relationship. | Chin Ngai Sze, Yu-Liang Wu |
| 2001 | Investigating the effect of voltage-switching on low-energy task scheduling in hard real-time systems. | Vishnu Swaminathan, Krishnendu Chakrabarty |
| 2001 | A higher level system communication model for object-oriented specification and design of embedded systems. | Kjetil Svarstad, Nezih Ben-Fredj, Gabriela Nicolescu, Ahmed Amine Jerraya |
| 2001 | An on-chip 96.5% current efficiency CMOS linear regulator. | Kazuhisa Sunaga, Tetsuo Endoh, Hiroshi Sakuraba, Fujio Masuoka |
| 2001 | A computer aided engineering system for memory BIST. | Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee |
| 2001 | Timing driven gate duplication in technology independent phase. | Ankur Srivastava, Chunhong Chen, Majid Sarrafzadeh |
| 2001 | Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits. | Nattha Sretasereekul, Takashi Nanya |
| 2001 | Reducing bus delay in submicron technology using coding. | Paul-Peter Sotiriadis, Anantha P. Chandrakasan |
| 2001 | High-level design for asynchronous logic. | Ross Smith, Michiel M. Ligthart |
| 2001 | Cellular automata as a built in self test structure. | Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri |
| 2001 | The multiple variable order problem for binary decision diagrams: theory and practical application. | Christoph Scholl, Bernd Becker, Andreas Brogle |
| 2001 | On the minimization of SOPs for bi-decomposition functions. | Tsutomu Sasao, Jon T. Butler |