| 2000 | Co-synthesis with custom ASICs. | Yuan Xie, Wayne H. Wolf |
| 2000 | Circuit partitioning with coupled logic restructuring techniques. | Yu-Liang Wu, Xiao-Long Yuan, David Ihsin Cheng |
| 2000 | Low-power design of sequential circuits using a quasi-synchronous derived clock. | Xunwei Wu, Jian Wei, Massoud Pedram, Qing Wu |
| 2000 | An interleaved dual-battery power supply for battery-operated electronics. | Qing Wu, Qinru Qiu, Massoud Pedram |
| 2000 | Power analysis and implementation of a low-power 300 MHz 8-b 8-b pipelined multiplier. | Jinn-Shyan Wang, Po-Hui Yang |
| 2000 | Integration of large-scale FPGA and DRAM in a package using chip-on-chip technology. | Michael X. Wang, Katsuharu Suzuki, Wayne Wei-Ming Dai, Yee L. Low, Kevin J. O'Conner, King L. Tai |
| 2000 | Modeling and minimization of routing congestion. | Maogang Wang, Majid Sarrafzadeh |
| 2000 | Multi-way partitioning using bi-partition heuristics. | Maogang Wang, Sung Kyu Lim, Jason Cong, Majid Sarrafzadeh |
| 2000 | Genetic algorithm accelerator GAA-II. | Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Masataka Yamane, Hajime Ueno |
| 2000 | Low-power design methodology and applications utilizing dual supply voltages. | Kimiyoshi Usami, Mutsunori Igarashi |
| 2000 | An interconnect topology optimization by a tree transformation. | Naofumi Tsujii, Katsutoshi Baba, Shuji Tsukiyama |
| 2000 | VLSI implementation of a switch fabric for mixed ATM and IP traffic. | Chi-Ying Tsui, Louis Chung-Yin Kwan, Chin-Tau Lea |
| 2000 | A testability metric for path delay faults and its application. | Huan-Chih Tsai, Kwang-Ting Cheng, Vishwani D. Agrawal |
| 2000 | An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). | Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2000 | Performance-optimal clustering with retiming for sequential circuits. | Tzu-Chieh Tien, Youn-Long Lin |
| 2000 | Embedded tutorial: subwavelength lithography. | Tsuneo Terasawa |
| 2000 | Symbolic circuit-noise analysis and modeling with determinant decision diagrams. | Xiang-Dong Tan, Chuanjin Richard Shi |
| 2000 | Design of self-timed asynchronous Booth's multiplier. | Tin-Y. Tang, Chiu-sing Choy, Pui-Lam Siu, Cheong-Fat Chan |
| 2000 | High performance of short-channel MOSFETs due to an elevated central-channel doping. | Masayasu Tanaka, N. Tokida, T. Okagaki, Mitiko Miura-Mattausch, Walter Hansch, Hans Jrgen Mattausch |
| 2000 | A smart imager for the vision processing front-END. | Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata |
| 2000 | Thread partitioning method for hardware compiler bach. | Mizuki Takahashi, Nagisa Ishiura, Akihisa Yamada, Takashi Kambe |
| 2000 | A new encoding scheme for rectangle packing problem. | Toshihiko Takahashi |
| 2000 | System-in-package (SIP): challenges and opportunities. | King L. Tai |
| 2000 | Importance of CAD tools and methodology in high speed CPU design: invited talk. | Haruyuki Tago, Kazuhiro Hashimoto, Nobuyuki Ikumi, Masato Nagamatsu, Masakazu Suzuoki, Yasuyuki Yamamoto |
| 2000 | Data transmission over a bus with peak-limited transition activity. | Vijay Sundararajan, Keshab K. Parhi |