| 2001 | Functional extension of structural logic optimization techniques. | Jos Alberto Espejo, Luis Entrena, Enrique San Milln, Emilio Olas |
| 2001 | New directions in compiler technology for embedded systems (embedded tutorial). | Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama, Ashok Halambi |
| 2001 | Provably good global buffering by multi-terminal multicommodity flow approximation. | Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky |
| 2001 | VLSI block placement using less flexibility first principles. | Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu |
| 2001 | On-chip interconnections: impact of adjacent lines on timing. | Denis Deschacht, Grgory Servel |
| 2001 | Improved crosstalk modeling for noise constrained interconnect optimization. | Jason Cong, David Zhigang Pan, Prasanna V. Srinivas |
| 2001 | A 3-step approach for performance-driven whole-chip routing. | Yih-Chih Chou, Youn-Long Lin |
| 2001 | Hierarchical dummy fill for process uniformity. | Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky |
| 2001 | Parameterized MAC unit implementation. | Ming-Chih Chen, Ing-Jer Huang, Chung-Ho Chen |
| 2001 | Low power techniques for address encoding and memory allocation. | Wei-Chung Cheng, Massoud Pedram |
| 2001 | Toward better wireload models in the presence of obstacles. | Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt |
| 2001 | Equivalence checking of integer multipliers. | Jiunn-Chern Chen, Yirng-An Chen |
| 2001 | Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers. | Subash Chandar G., S. Vaideeswaran |
| 2001 | An efficient solution to the storage correspondence problem for large sequential circuits. | Wanlin Cao, D. M. H. Walker, Rajarshi Mukherjee |
| 2001 | RPack: routability-driven packing for cluster-based FPGAs. | Elaheh Bozorgzadeh, Seda Ogrenci Memik, Majid Sarrafzadeh |
| 2001 | Low power design challenges for the decade (invited talk). | Shekhar Borkar |
| 2001 | Synthesis of single-output space compactors with application to scan-based IP cores. | Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gssel, Krishnendu Chakrabarty |
| 2001 | Device-level placement for analog layout: an opportunity for non-slicing topological representations. | Florin Balasa |
| 2001 | Multi-hit time-to-digital converter VLSI for high-energy physics experiments. | Yasuo Arai |
| 2001 | Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points. | Amir H. Ajami, Massoud Pedram |
| 2000 | MMP: a novel placement algorithm for combined macro block and standard cell layout design. | Hong Yu, Xianlong Hong, Yici Cai |
| 2000 | A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation. | Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng |
| 2000 | Area routing oriented hierarchical corner stitching with partial bin. | Yan Zhang, Baohua Wang, Yici Cai, Xianlong Hong |
| 2000 | An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation. | Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya |
| 2000 | Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk. | Masakazu Yamashina, Masato Motomura |