| 1999 | A Genetic Algorithm based Approach for Multi-Objective Data-Flow Graph Optimization. | Birger Landwehr |
| 1999 | Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment. | Marcello Lajolo, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
| 1999 | A New Single-Clock Flip-Clop for Half-Swing Clocking. | Young-Su Kwon, Bong-Il Park, In-Cheol Park, Chong-Min Kyung |
| 1999 | Combining Speculative Execution and Conditional Resource Sharing to Efficiently Schedule Conditional Behaviors. | Apostolos A. Kountouris, Christophe Wolinski |
| 1999 | Formal Verification Method for Combinatorial Circuits at High Level Design. | Junji Kitamichi, Hiroyuki Kageyama, Nobuo Funabiki |
| 1999 | 16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony. | Tae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee, Hyoung Sik Nam, Young Gon Kim, Jeong Pyo Kim, Sangjin Byun, Bae Sung Kwon, Beomsup Kim |
| 1999 | An 8b 52MHz Double-Channel CMOS A/D Converter for High-Speed Data Communications. | Ju-Hyung Kim, Sung-Wook Hwang, Seung-Hoon Lee, Yong Jee |
| 1999 | Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. | Martin Keim, Nicole Drechsler, Bernd Becker |
| 1999 | Optimization of Linear Placements for Wirelength Minimization with Free Sites. | Andrew B. Kahng, Paul Tucker, Alexander Zelikovsky |
| 1999 | New Multilevel and Hierarchical Algorithms for Layout Density Control. | Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky |
| 1999 | A New Pipelined Architecture for Fuzzy Color Correction. | Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau |
| 1999 | A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform. | Jer-Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Ming-Shiang Liang |
| 1999 | Waveform Relaxation of Linear Integral-Differential Equations for Circuit Simulation. | Yao-Lin Jiang, Omar Wing |
| 1999 | Motion Estimator LSI for MPEG2 High Level Standard. | Li Jiang, Dongju Li, Shintaro Haba, Chawalit Honsawek, Hiroaki Kunieda |
| 1999 | A 10b 50 MHz CMOS A/D Converter for High-Speed Video Applications. | Byeong-Lyeol Jeon, Kang-Jin Lee, Seung-Hoon Lee, Sang-Won Yoon |
| 1999 | Realization of Regular Ternary Logic Functions. | Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno |
| 1999 | A Timing-Driven Block Placer Based on Sequence Pair Model. | Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai |
| 1999 | The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance. | Jinsong Hou, Zeyi Wang, Xianlong Hong |
| 1999 | Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. | Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide |
| 1999 | Minimization of Free BDDs. | Wolfgang Gnther, Rolf Drechsler |
| 1999 | A New Numerical Method for Transient Noise Analysis of Nonlinear Circuits. | Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney |
| 1999 | A New Technique to Exploit Frequency Domain Latency in Harmonic Balance Simulators. | Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney |
| 1999 | Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model. | Youxin Gao, D. F. Wong |
| 1999 | A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs. | Wen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu |
| 1999 | An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures. | C. K. Eem, J. W. Chong |