| 1999 | Exploiting Don't Caers During Data Sequencing using Genetic Algorithms. | Rolf Drechsler, Nicole Drechsler |
| 1999 | On the Testing Quality of Random and Pseudo-random Sequences for Permanent and Intermittent Faults. | Jin Ding, Yu-Liang Wu |
| 1999 | Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis. | Nagu R. Dhanwada, Adrin Nez-Aldana, Ranga Vemuri |
| 1999 | Fast Boolean Matching Under Permutation Using Representative. | Debatosh Debnath, Tsutomu Sasao |
| 1999 | Interconnect Delay Estimation Models for Synthesis and Design Planning. | Jason Cong, David Zhigang Pan |
| 1999 | Relaxed Simulated Tempering for VLSI Floorplan Designs. | Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong |
| 1999 | The Design of Delay Insensitive Asynchronous 16-bit Microprocessor. | Byung-Soo Choi, Dong-Wook Lee, Dong-Ik Lee |
| 1999 | Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods. | Hoon Choi, Hansoo Kim, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung |
| 1999 | An Efficient Two-Level Partitioning Algorithm for VLSI Circuits. | Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho |
| 1999 | Timing Optimization of Logic Network Using Gate Duplication. | Chun-hong Chen, Chi-Ying Tsui |
| 1999 | Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. | Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau |
| 1999 | Electronics Development of Silicon Microdisplay for Virtual Reality Applications. | P. W. Cheng, H. C. Huang |
| 1999 | An Automatic Router for the Pin Grid Array Package. | Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai |
| 1999 | Watermarking Layout Topologies. | Edoardo Charbon, Ilhami Torunoglu |
| 1999 | Faster and Better Spectral Algorithms for Multi-Way Partitioning. | Jan-Yang Chang, Yu-Chen Liu, Ting-Chi Wang |
| 1999 | Universal Switched-Current Integrator Blocks for SI Filter Design. | Jack L. Chan, Steve S. Chung |
| 1999 | Symmetry Detection for Automatic Analog-Layout Recycling. | Youcef Bourai, Chuanjin Richard Shi |
| 1999 | FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. | Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong |
| 1999 | A New Global Routing Algorithm Independent Of Net Ordering. | Haiyun Bao, Xianlong Hong, Yici Cai |
| 1999 | Function Smoothing with Applications to VLSI Layout. | Ross Baldick, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov |
| 1998 | FPART: A Multi-way FPGA Partitioning Procedure Based on the Improved FM Algorithm. | Rongzheng Zhou, Jiarong Tong, Pushan Tang |
| 1998 | Design of Nonlinear Switched-Current Circuits Using Building Block Approach. | X. Zeng, P. S. Tang, C. K. Tse |
| 1998 | An Efficient Variable-Length Tap FIR Filter Chip. | Sung Hyun Yoon, Myung Hoon Sunwoo |
| 1998 | A ±1.5V 4MHz Low-Pass Gm-C Filter in CMOS. | Changsik Yoo, Wonchan Kim |
| 1998 | A Top-down Hardware/Software Co-Simulation Method for Embedded Systems Based Upon a Component Logical Bus Architecture. | Mitsuhiro Yasuda, Katsuhiko Seo, Hisao Koizumi, Barry Shackleford, Fumio Suzuki |