| 1997 | Acceleration of mincut partitioning using hardware CAD accelerator TP5000. | Masahiro Sano, Shintaro Shimogori, Fumiyasu Hirose |
| 1997 | A two-dimensional transistor placement for cell synthesis. | Shunji Saika, Masahiro Fukui, Noriko Shinomiya, Toshiro Akino |
| 1997 | A new linear-time harmonic balance algorithm for cyclostationary noise analysis in RF circuits. | Jaijeet S. Roychowdhury, Peter Feldmann |
| 1997 | A new description of CMOS circuits at switch-level. | Massoud Pedram, Xunwei Wu |
| 1997 | Trade-off evaluation in embedded system design via co-simulation. | Claudio Passerone, Luciano Lavagno, Claudio Sanso, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli |
| 1997 | Performance test of Viterbi decoder for wideband CDMA system. | Jang-Hyun Park, Yea-Chul Rho |
| 1997 | Power consumption in CMOS combinational logic blocks at high frequencies. | Sri Parameswaran, Hui Guo |
| 1997 | Self-timed 1-D ICT processor. | Tin-Chak Johnson Pang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Wai-kuen Cham |
| 1997 | A time-domain method for numerical noise analysis of oscillators. | Makiko Okumura, Hiroshi Tanimoto |
| 1997 | The RDT network router chip. | Hiroaki Nishi, Hideharu Amano, Katsunobu Nishimura, Kenichiro Anjo, Tomohiro Kudoh |
| 1997 | VLSI implementation of a real-time operating system. | Takumi Nakano, Yoshiki Komatsudaira, Akichika Shiomi, Masaharu Imai |
| 1997 | A mapping from sequence-pair to rectangular dissection. | Hiroshi Murata, Kunihiro Fujiyoshi, Tomomi Watanabe, Yoji Kajitani |
| 1997 | Advanced processor design using hardware description language AIDL. | Takayuki Morimoto, Kazushi Saito, Hiroshi Nakamura, Taisuke Boku, Kisaburo Nakazawa |
| 1997 | A high performance FIR filter dedicated to digital video transmission. | Shun Morikawa, Keisuke Okada, Sumitaka Takeuchi, Isao Shirakawa |
| 1997 | Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system. | Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka |
| 1997 | Crosstalk noise in high density and high speed interconnections due to inductive coupling. | Tetsuhisa Mido, Kunihiro Asada |
| 1997 | Built-in chaining: introducing complex components into architectural synthesis. | Peter Marwedel, Birger Landwehr, Rainer Dmer |
| 1997 | Processor-core based design and test. | Peter Marwedel |
| 1997 | Adaptive models for input data compaction for power simulators. | Radu Marculescu, Diana Marculescu, Massoud Pedram |
| 1997 | A new layout-driven timing model for incremental layout optimization. | Fang-Jou Liu, John Lillis, Chung-Kuan Cheng |
| 1997 | Computing brokerage and its application in VLSI design. | Youn-Long Lin |
| 1997 | Optimal loop bandwidth design for low noise PLL applications. | Kyoohyun Lim, Seung Hee Choi, Beomsup Kim |
| 1997 | Logic synthesis for cellular architecture FPGAs using BDDs. | Gueesang Lee |
| 1997 | Multi-project chip activities in Korea-IDEC perspective. | Chong-Min Kyung, In-Cheol Park, Ho-Jun Song |
| 1997 | HK386: an x86-compatible 32-bit CISC microprocessor. | Chong-Min Kyung, In-Cheol Park, Se-Kyoung Hong, K. S. Seong, B. S. Kong, Seungjong Lee, Hoon Choi, S. R. Maeng, D. T. Kim, Jong-Sun Kim, S. H. Park, Y. J. Kang |