| 1997 | Single cycle access cache for the misaligned data and instruction prefetch. | Joon-Seo Yim, Hee-Choul Lee, Tae-Hoon Kim, Bong-Il Park, Chang-Jae Park, In-Cheol Park, Chong-Min Kyung |
| 1997 | Efficient synthesis of AND/XOR networks. | Yibin Ye, Kaushik Roy |
| 1997 | Architecture evaluation based on the datapath structure and parallel constraint. | Masayuki Yamaguchi, Akihisa Yamada, Toshihiro Nakaoka, Takashi Kambe |
| 1997 | ChipEst-FPGA: a tool for chip level area and timing estimation of lookup table based FPGAs for high level applications. | Min Xu, Fadi J. Kurdahi |
| 1997 | A note on the relationship between signal probability and switching activity. | Qing Wu, Massoud Pedram, Xunwei Wu |
| 1997 | Statistical design of macro-models for RT-level power evaluation. | Qing Wu, Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram |
| 1997 | Not necessarily more switches more routability [sic.]. | Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, Shuji Tsukiyama |
| 1997 | MULTI-PRIDE: a system for supporting multi-layered printed wiring board design. | Toshimasa Watanabe |
| 1997 | A constructive method for data path area estimation during high-level VLSI synthesis. | Natesan Venkateswaran, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia, Ranga Vemuri |
| 1997 | RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking. | Vida Vakilotojar, Peter A. Beerel |
| 1997 | Fuzzy-based circuit partitioning in built-in current testing. | Wang-Dauh Tseng, Kuochen Wang |
| 1997 | A power driven two-level logic optimizer. | Jyh-Mou Tseng, Jing-Yang Jou |
| 1997 | A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. | Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki |
| 1997 | Delay estimation for technology independent synthesis. | Yutaka Tamiya |
| 1997 | Super low power 8-bit CPU with pass-transistor logic. | Kazuo Taki, Bu-Yeol Lee, Hideki Tanaka, Kenzo Konishi |
| 1997 | Performance and reliability driven clock scheduling of sequential logic circuits. | Atsushi Takahashi, Yoji Kajitani |
| 1997 | Non-scan design for testable data paths using thru operation. | Katsuyuki Takabatake, Toshimitsu Masuzawa, Michiko Inoue, Hideo Fujiwara |
| 1997 | A current-mode, 3 V, 20 MHz, 9-bit equivalent CMOS sample-and-hold circuit. | Yasuhiro Sugimoto, Tetsuya Iida |
| 1997 | Structural approach for performance driven ECC circuit synthesis. | Chauchin Su, Kathy Y. Chen, Shyh-Jye Jou |
| 1997 | AND/OR reasoning graphs for determining prime implicants in multi-level combinational networks. | Dominik Stoffel, Wolfgang Kunz, Stefan Gerber |
| 1997 | Solving constrained via minimization by compact linear programming. | C.-J. Richard Shi |
| 1997 | Block-level fault isolation using partition theory and logic minimization techniques. | C.-J. Richard Shi |
| 1997 | CB-Power: a hierarchical cell-based power characterization and estimation environment for static CMOS circuits. | Wen-Zen Shen, Jiing-Yuan Lin, Jyh-Ming Lu |
| 1997 | CBLO: a clustering based linear ordering for netlist partitioning. | Kwang-Su Seong, Chong-Min Kyung |
| 1997 | Modeling and detection of dynamic errors due to reflection- and crosstalk-noise. | Jrgen Schrage |