| 1998 | Motion Adaptive Image Sensor. | Takayuki Hamamoto, Kiyoharu Aizawa, Mitsutoshi Hatori |
| 1998 | Curvilinear Detailed Routing Algorithm and Its Extension to Wire-Spreading and Wire-Fattening. | Toshiyuki Hama, Hiroaki Etoh |
| 1998 | Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines. | Hui Guo, Sri Parameswaran |
| 1998 | Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis. | S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, Donald Cottrell, David Mallis, S. DasGupta, Joseph Morrell, J. Sayah, R. Gupta, P. T. Patel, P. Adams |
| 1998 | A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling. | Seiji Funaba, Akihiro Kitagawa, Toshiro Tsukada, Goichi Yokomizo |
| 1998 | Model Checking: Its Basics and Reality (Embedded Tutorial). | Masahiro Fujita |
| 1998 | Concurrent Technology, Device, and Circuit Development for EEPROMs. | Ute Feldmann, Ronald Kakoschke, Mitiko Miura-Mattausch, G. Schraud |
| 1998 | An Effcient 2-D Convolver Chip for Real Time Image Processing. | Se Young Eun, Myung Hoon Sunwoo |
| 1998 | Pre-layout Delay Calculation Specification for CMOS ASIC Libraries. | Hisakazu Edamatsu, Katsumi Homma, Masaru Kakimoto, Yutaka Koike, Kinya Tabuchi |
| 1998 | Manipulation of *BMDs. | Rolf Drechsler, Stefan Hreth |
| 1998 | Considering Testability during High-level Design (Embedded Tutorial). | Sujit Dey, Anand Raghunathan, Rabindra K. Roy |
| 1998 | Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial). | Anirudh Devgan, Sandip Kundu |
| 1998 | A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks. | Debatosh Debnath, Tsutomu Sasao |
| 1998 | Interchangeable Boolean Functions and Their Effects on Redundancy in Logic Circuits. | Debesh K. Das, Susanta Chakraborty, Bhargab B. Bhattacharya |
| 1998 | CHDStd - A Model for Deep Submicron Design Tools. | Donald Cottrell, David Mallis, Joseph Morrell |
| 1998 | A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm. | Liang-Gee Chen, Juing-Ying Jiu, Hao-Chieh Chang, Yung-Pin Lee, Chung-Wei Ku |
| 1998 | A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. | Nguyen-Ngoc Bnh, Masaharu Imai, Yoshinori Takeuchi |
| 1998 | A Low Power 50MHz FFT Processor with Cyclic Extension and Shaping Filter. | Mark A. Bickerstaff, T. Arivoli, Philip J. Ryan, Neil Weste, David J. Skellern |
| 1998 | Software Licensing Models in the EDA Industry. | Dinesh R. Bettadapur |
| 1998 | Parallelization in Co-Compilation for Configurable Accelerators. | Jrgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger |
| 1998 | Reconfigurable Systems: Activities in Asia and South Pacific (Embedded Tutorial). | Hideharu Amano, Yuichiro Shibata |
| 1998 | ATM Cell Modelling using Objective VHDL. | Alberto Allara, Massimo Bombana, Patrizia Cavalloro, Wolfgang Nebel, Wolfram Putzke-Rming, Martin Radetzki |
| 1997 | Parallel calculation of 3-D parasitic resistance and capacitance with linear boundary elements. | Wenming Zhou, Zeyi Wang, Lan Rao |
| 1997 | An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits. | Kai Zhang, Haruhiko Takase, Terumine Hayashi, Hidehiko Kita |
| 1997 | Verification methodology of compatible microprocessors. | Joon-Seo Yim, Chang-Jae Park, Woo-Seung Yang, Hun-Seung Oh, Hee-Choul Lee, Hoon Choi, Tae-Hoon Kim, Seungjong Lee, Nara Won, Yung-Hei Lee, In-Cheol Park, Chong-Min Kyung |