| 1997 | A procedure for software synthesis from VHDL models. | Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee |
| 1997 | Collaboration between university and industry. | Tokinori Kozawa |
| 1997 | VEAP: Global optimization based efficient algorithm for VLSI placement. | Tianming Kong, Xianlong Hong, Changge Qiao |
| 1997 | A current mode cyclic A/D converter with a 0.8 μm CMOS process. | Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru |
| 1997 | Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs. | Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru |
| 1997 | A functional memory type parallel processor for vector quantization. | Kazutoshi Kobayashi, Masayoshi Kinoshita, Masahiro Takeuchi, Hidetoshi Onodera, Keikichi Tamaru |
| 1997 | A CMOS delayed locked loop (DLL) for reducing clock skew to under 500 ps. | Yong-Bin Kim, Tom Chen |
| 1997 | General floorplanning with L-shaped, T-shaped and soft blocks based on bounded slicing grid structure. | Maggie Zhiwei Kang, Wayne Wei-Ming Dai |
| 1997 | Concurrent cell generation and mapping for CMOS logic circuits. | M. Kanecko, Jialin Tian |
| 1997 | An LSI implementation of the simple serial synchronized multistage interconnection network. | Takayuki Kamei, Masashi Sasahara, Hideharu Amano |
| 1997 | EMC-adequate design of printed circuit boards as a part of the system development. | Werner John |
| 1997 | BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. | Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei |
| 1997 | Embedded architectural simulation within behavioral synthesis environment. | Abderrazek Jemai, Polen Kission, Ahmed Amine Jerraya |
| 1997 | High speed bit-serial parallel processing on array architecture. | Kazuhito Ito, Takenobu Shimizugashira, Hiroaki Kunieda |
| 1997 | A hardware/software co-simulation environment for micro-processor design with HDL simulator and OS interface. | Yoshiyuki Ito, Yuichi Nakamura |
| 1997 | Bit-serial pipeline synthesis and layout for large-scale configurable systems. | Tsuyoshi Isshiki, Wayne Wei-Ming Dai, Hiroaki Kunieda |
| 1997 | Efficient routability checking for global wires in planar layouts. | Naoyuki Iso, Yasushi Kawaguchi, Tomio Hirata |
| 1997 | Evaluating cost-performance tradeoffs for system level applications. | Wei-Liang Ing, Cheng-Tsung Hwang, Allen C.-H. Wu |
| 1997 | On properties of Kleene TDDs. | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura |
| 1997 | On the control-subroutine implementation of subprogram synthesis. | Cheng-Tsung Hwang, Hsiao-Chien Weng, Yu-Chin Hsu, Mike Tien-Chien Lee |
| 1997 | An entropy measure for power estimation of Boolean functions. | Chi-Hong Hwang, Allen C.-H. Wu |
| 1997 | Multi-project chip service for university and industry in Taiwan. | Jen-Sheng Hwang |
| 1997 | Synthesis and analysis of an industrial embedded microcontroller. | Ing-Jer Huang, Li-Rong Wang, Yu-Min Wang |
| 1997 | AQUILA: An equivalence verifier for large sequential circuits. | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen |
| 1997 | A quantitative analysis for optimizing memory allocation. | Youn-Sik Hong, Choong-Hee Cho, Daniel D. Gajski |