| 2013 | Optimizing translation information management in NAND flash memory storage systems. | Qi Zhang, Xuandong Li, Linzhang Wang, Tian Zhang, Yi Wang, Zili Shao |
| 2013 | Sequential dependency and reliability analysis of embedded systems. | Hehua Zhang, Yu Jiang, Xiaoyu Song, William N. N. Hung, Ming Gu, Jiaguang Sun |
| 2013 | Piecewise-polynomial associated transform macromodeling algorithm for fast nonlinear circuit simulation. | Yang Zhang, Neric Fong, Ngai Wong |
| 2013 | A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS. | Xin Zhang, Po-Hung Chen, Yoshikatsu Ryu, Koichi Ishida, Yasuyuki Okuma, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya |
| 2013 | An efficient hybrid synchronization technique for scalable multi-core instruction set simulations. | Bo-Han Zeng, Ren-Song Tsay, Ting-Chi Wang |
| 2013 | An ultra-compact virtual source FET model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuits. | Li Yu, Omar Mysore, Lan Wei, Luca Daniel, Dimitri A. Antoniadis, Ibrahim M. Elfadel, Duane S. Boning |
| 2013 | L-shape based layout fracturing for e-beam lithography. | Bei Yu, Jhih-Rong Gao, David Z. Pan |
| 2013 | A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. | Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro |
| 2013 | A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. | Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2013 | A binding algorithm in high-level synthesis for path delay testability. | Yuki Yoshikawa |
| 2013 | Simplification of C-RTL equivalent checking for fused multiply add unit using intermediate models. | Bin Xue, Prosenjit Chatterjee, Sandeep K. Shukla |
| 2013 | VFCC: A verification framework of cache coherence using parallel simulation. | Qiaoli Xiong, Jiangfang Yi, Tianbao Song, Zichao Xie, Dong Tong |
| 2013 | An efficient scheduling algorithm for multiple charge migration tasks in hybrid electrical energy storage systems. | Qing Xie, Di Zhu, Yanzhi Wang, Massoud Pedram, Younghyun Kim, Naehyuck Chang |
| 2013 | Network flow modeling for escape routing on staggered pin arrays. | Pei-Ci Wu, Martin D. F. Wong |
| 2013 | An ILP-based automatic bus planner for dense PCBs. | Pei-Ci Wu, Qiang Ma, Martin D. F. Wong |
| 2013 | Improving the mapping of reversible circuits to quantum circuits using multiple target lines. | Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler |
| 2013 | Loadsa: A yield-driven top-down design method for STT-RAM array. | Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran Chen |
| 2013 | Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. | Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert |
| 2013 | Scratchpad Memory aware task scheduling with minimum number of preemptions on a single processor. | Qing Wan, Hui Wu, Jingling Xue |
| 2013 | Optimizing multi-level combinational circuits for generating random bits. | Chen Wang, Weikang Qian |
| 2013 | Power optimization for application-specific 3D network-on-chip with multiple supply voltages. | Kan Wang, Sheqin Dong |
| 2013 | A network-flow based valve-switching aware binding algorithm for flow-based microfluidic biochips. | Kai-Han Tseng, Sheng-Chi You, Wajid Hassan Minhass, Tsung-Yi Ho, Paul Pop |
| 2013 | Heterogeneous memory management for 3D-DRAM and external DRAM with QoS. | Le-Nguyen Tran, Fadi J. Kurdahi, Ahmed M. Eltawil, Houman Homayoun |
| 2013 | SMYLE OpenCL: A programming framework for embedded many-core SoCs. | Hiroyuki Tomiyama, Takuji Hieda, Naoki Nishiyama, Noriko Etani, Ittetsu Taniguchi |
| 2013 | 2.5D design methodology. | Shinya Tokunaga |