| 2013 | HS3DPG: Hierarchical simulation for 3D P/G network. | Shuai Tao, Xiaoming Chen, Yu Wang, Yuchun Ma, Yiyu Shi, Hui Wang, Huazhong Yang |
| 2013 | Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme. | Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi |
| 2013 | Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression. | Chao Sun, Hiroki Fujii, Kousuke Miyaji, Koh Johguchi, Kazuhide Higuchi, Ken Takeuchi |
| 2013 | A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13m CMOS process. | Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Inhwa Jung, Chulwoo Kim |
| 2013 | Stable backward reachability correction for PLL verification with consideration of environmental noise induced jitter. | Yang Song, Haipeng Fu, Hao Yu, Guoyong Shi |
| 2013 | A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption. | Kenta Sogo, Akihiro Toya, Takamaro Kikkawa |
| 2013 | A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers. | Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa |
| 2013 | Secure storage system and key technologies. | Jiwu Shu, Zhirong Shen, Wei Xue, Yingxun Fu |
| 2013 | An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation. | Michihiro Shintani, Takashi Sato |
| 2013 | Online estimation of the remaining energy capacity in mobile systems considering system-wide power consumption and battery characteristics. | Donghwa Shin, Kitae Kim, Naehyuck Chang, Woojoo Lee, Yanzhi Wang, Qing Xie, Massoud Pedram |
| 2013 | Symmetrical buffered clock-tree synthesis with supply-voltage alignment. | Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao |
| 2013 | Power distribution network modeling for 3-D ICs with TSV arrays. | Chi-Kai Shen, Yi-Chang Lu, Yih-Peng Chiou, Tai-Yu Cheng, Tzong-Lin Wu |
| 2013 | Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model. | Yang Shang, Chun Zhang, Hao Yu, Chuan Seng Tan, Xin Zhao, Sung Kyu Lim |
| 2013 | Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon via. | Tadatoshi Sekine, Hideki Asai |
| 2013 | A computational model for SAT-based verification of hardware-dependent low-level embedded system software. | Bernard Schmidt, Carlos Villarraga, Jrg Bormann, Dominik Stoffel, Markus Wedler, Wolfgang Kunz |
| 2013 | Provably optimal test cube generation using quantified boolean formula solving. | Matthias Sauer, Sven Reimer, Ilia Polian, Tobias Schubert, Bernd Becker |
| 2013 | Schedule integration for time-triggered systems. | Florian Sagstetter, Martin Lukasiewycz, Samarjit Chakraborty |
| 2013 | Hardware security strategies exploiting nanoelectronic circuits. | Garrett S. Rose, Jeyavijayan Rajendran, Nathan R. McDonald, Ramesh Karri, Miodrag Potkonjak, Bryant T. Wysocki |
| 2013 | Reliability assessment of safety-relevant automotive systems in a model-based design flow. | Sebastian Reiter, Michael Pressler, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel |
| 2013 | Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects. | Hanhua Qian, Hao Liang, Chip-Hong Chang, Wei Zhang, Hao Yu |
| 2013 | Implementing microprocessors from simplified descriptions. | Nikhil A. Patil, Derek Chiou |
| 2013 | High-density integration of functional modules using monolithic 3D-IC technology. | Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim |
| 2013 | I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs. | Chi-Wen Pan, Yu-Min Lee, Pei-Yu Huang, Chi-Ping Yang, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai |
| 2013 | Dependable VLSI Platform using Robust Fabrics. | Hidetoshi Onodera |
| 2013 | A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells. | Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto |