| 2012 | Performance estimation of embedded software with confidence levels. | Marco Lattuada, Fabrizio Ferrandi |
| 2012 | Predictor-corrector latency insertion method for fast transient analysis of ill-constructed circuits. | Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai |
| 2012 | Thread affinity mapping for irregular data access on shared Cache GPGPU. | Hsien-Kai Kuo, Kuan-Ting Chen, Bo-Cheng Charles Lai, Jing-Yang Jou |
| 2012 | Verifying dynamic power management schemes using statistical model checking. | Jayanand Asok Kumar, Shobha Vasudevan |
| 2012 | A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18m CMOS. | Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera |
| 2012 | Micro-bump assignment for 3D ICs using order relation. | Ta-Yu Kuan, Yi-Chun Chang, Tai-Chen Chen |
| 2012 | An any-angle routing method using quasi-Newton method. | Yukihide Kohira, Atsushi Takahashi |
| 2012 | Body bias clustering for low test-cost post-silicon tuning. | Shuta Kimura, Masanori Hashimoto, Takao Onoye |
| 2012 | Block-level 3D IC design with through-silicon-via planning. | Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim |
| 2012 | Algorithm for synthesizing design context-aware fast carry-skip adders. | Kiyoung Kim, Taewhan Kim |
| 2012 | The feasibility of Carbon Nanotubes for power delivery in 3-D Integrated Circuits. | Nauman H. Khan, Soha Hassoun |
| 2012 | Using link-level latency analysis for path selection for real-time communication on NoCs. | Hany Kashif, Hiren D. Patel, Sebastian Fischmeister |
| 2012 | Post silicon skew tuning: Survey and analysis. | Mac Y. C. Kao, Kun-Ting Tsai, Hsuan-Ming Chou, Shih-Chieh Chang |
| 2012 | A learning-based autoregressive model for fast transient thermal analysis of chip-multiprocessors. | Da-Cheng Juan, Huapeng Zhou, Diana Marculescu, Xin Li |
| 2012 | Design-patterning co-optimization of SRAM robustness for double patterning lithography. | Vivek Joshi, Kanak Agarwal, Dennis Sylvester |
| 2012 | CMA-2 : The second prototype of a low power reconfigurable accelerator. | Mai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura |
| 2012 | Accelerator-rich architectures: Implications, opportunities and challenges. | Ravi R. Iyer |
| 2012 | Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range. | Keisuke Inoue, Mineo Kaneko |
| 2012 | System-wide profiling and optimization with virtual machines. | Shih-Hao Hung, Tei-Wei Kuo, Chi-Sheng Shih, Chia-Heng Tu |
| 2012 | On-chip statistical hot-spot estimation using mixed-mesh statistical polynomial expression generating and skew-normal based moment matching techniques. | Pei-Yu Huang, Yu-Min Lee, Chi-Wen Pan |
| 2012 | On-line leakage-aware energy minimization scheduling for hard real-time systems. | Huang Huang, Ming Fan, Gang Quan |
| 2012 | Crosstalk-aware power optimization with multi-bit flip-flops. | Chih-Cheng Hsu, Yao-Tsung Chang, Mark Po-Hung Lin |
| 2012 | Clock rescheduling for timing engineering change orders. | Kuan-Hsien Ho, Xin-Wei Shih, Jie-Hong R. Jiang |
| 2012 | Design techniques for functional-unit power gating in the Ultra-Low-Voltage region. | Michael B. Henry, Leyla Nazhandali |
| 2012 | Invasive manycore architectures. | Jrg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hbner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe |