Design, Automation and Test in Europe Conference
DATE
A
CORE rank
CORE rank (raw)
A
Fields of research
Computer Systems Engineering · Software Engineering
Papers indexed
9,217
1995–2026
Papers per year
1995445 peak2026
Most published authors
DATE papers
9,217 records sourced from DBLP. Search titles, filter by year, sort by recency.
| Year | Title | Authors |
|---|---|---|
| 2018 | Compiler-driven error analysis for designing approximate accelerators. | Jorge Castro-Godnez, Sven Esser, Muhammad Shafique, Santiago Pagani, Jrg Henkel |
| 2018 | ERASMUS: Efficient remote attestation via self-measurement for unattended settings. | Xavier Carpent, Gene Tsudik, Norrathep Rattanavipanon |
| 2018 | PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks. | Alexandre Carbon, Jean-Marc Philippe, Olivier Bichler, Renaud Schmit, Benot Tain, David Briand, Nicolas Ventroux, Michel Paindavoine, Olivier Brousse |
| 2018 | Characterization of possibly detected faults by accurately computing their detection probability. | Jan Burchard, Dominik Erb, Bernd Becker |
| 2018 | Optimal metastability-containing sorting networks. | Johannes Bund, Christoph Lenzen, Moti Medina |
| 2018 | OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation. | Robert Lajos Bcs, Maximilian Fricke, Rainer Leupers, Gerd Ascheid, Stephan Tobies, Andreas Hoffmann |
| 2018 | SCADPA: Side-channel assisted differential-plaintext attack on bit permutation based ciphers. | Jakub Breier, Dirmanto Jap, Shivam Bhasin |
| 2018 | Approximate quaternary addition with the fast carry chains of FPGAs. | Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk |
| 2018 | Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solution. | Thierry Bonnoit, Fraidy Bouesse, Nacer-Eddine Zergainoh, Michael Nicolaidis |
| 2018 | dReDBox: Materializing a full-stack rack-scale system prototype of a next-generation disaggregated datacenter. | Maciej Bielski, Ilias Syrigos, Kostas Katrinis, Dimitris Syrivelis, Andrea Reale, Dimitris Theodoropoulos, Nikolaos Alachiotis, Dionisis N. Pnevmatikatos, E. H. Pap, George Zervas, Vaibhawa Mishra, Arsalan Saljoghei, Alvise Rigo, Jose Fernando Zazo, Sergio Lpez-Buedo, Mart Torrents, Ferad Zyulkyarov, Michael Enrico, scar Gonzlez de Dios |
| 2018 | Storage-aware sample preparation using flow-based microfluidic Labs-on-Chip. | Sukanta Bhattacharjee, Robert Wille, Juinn-Dar Huang, Bhargab B. Bhattacharya |
| 2018 | Technology-aware logic synthesis for ReRAM based in-memory computing. | Debjyoti Bhattacharjee, Luca G. Amar, Anupam Chattopadhyay |
| 2018 | Advancing source-level timing simulation using loop acceleration. | Joscha Benz, Christoph Gerum, Oliver Bringmann |
| 2018 | Design and integration of hierarchical-placement multi-level caches for real-time systems. | Pedro Benedicte, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2018 | Airavat: Improving energy efficiency of heterogeneous applications. | Trinayan Baruah, Yifan Sun, Shi Dong, David R. Kaeli, Norm Rubin |
| 2018 | High-level synthesis of software-customizable floating-point cores. | Samridhi Bansal, Hsuan Hsiao, Tomasz S. Czajkowski, Jason Helge Anderson |
| 2018 | Trident: A comprehensive timing error resilient technique against choke points at NTC. | Aatreyi Bal, Sanghamitra Roy, Koushik Chakraborty |
| 2018 | LASER: A hardware/software approach to accelerate complicated loops on CGRAs. | Mahesh Balasubramanian, Shail Dave, Aviral Shrivastava, Reiley Jeyapaul |
| 2018 | Confident leakage assessment - A side-channel evaluation framework based on confidence intervals. | Florian Bache, Christina Plump, Tim Gneysu |
| 2018 | Computing with ferroelectric FETs: Devices, models, systems, and applications. | Ahmedullah Aziz, Evelyn T. Breyer, An Chen, Xiaoming Chen, Suman Datta, Sumeet Kumar Gupta, Michael Hoffmann, Xiaobo Sharon Hu, Adrian M. Ionescu, Matthew Jerry, Thomas Mikolajick, Halid Mulaosmanovic, Kai Ni, Michael T. Niemier, Ian O'Connor, Atanu Saha, Stefan Slesazeck, Sandeep Krishna Thirumala, Xunzhao Yin |
| 2018 | ORIENT: Organized interleaved ECCs for new STT-MRAM caches. | Zahra Azad, Hamed Farbeh, Amir Mahdi Hosseini Monazzah |
| 2018 | Binary Ring-LWE hardware with power side-channel countermeasures. | Aydin Aysu, Michael Orshansky, Mohit Tiwari |
| 2018 | zone: Efficient execution with zero timing leakage for modern microarchitectures. | Zelalem Birhanu Aweke, Todd M. Austin |
| 2018 | uSFI: Ultra-lightweight software fault isolation for IoT-class devices. | Zelalem Birhanu Aweke, Todd M. Austin |
| 2018 | Mixed-criticality scheduling with memory bandwidth regulation. | Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Akesson, Eduardo Tovar |
3,151–3,175 of 9,217← PreviousNext →
Comparable venues
Other A*/A conferences filed under the same field of research.
- A*DACDesign Automation Conf
- ASCInternational Conference for High Performance Computing, Networking, Storage and Analysis (was Supercomputing Conference)
- AICCADIEEE/ACM International Conference on Computer-Aided Design
- AITCIEEE International Test Conference
- A*ISCAACM International Symposium on Computer Architecture
- A*MICROInternational Symposium on Microarchitecture
- AISLPEDIEEE/ACM International Symposium on Low Power Electronics and Design
- AICSACM International Conference on Supercomputing