| 2015 | Sub-10 nm FinFETs and Tunnel-FETs: from devices to systems. | Ankit Sharma, A. Arun Goud, Kaushik Roy |
| 2015 | Minimum current consumption transition time optimization methodology for low power CTS. | Vibhu Sharma |
| 2015 | Variability-aware dark silicon management in on-chip many-core systems. | Muhammad Shafique, Dennis Gnad, Siddharth Garg, Jrg Henkel |
| 2015 | Formal analysis of the startup delay of SOME/IP service discovery. | Jan R. Seyler, Thilo Streichert, Michael Gla, Nicolas Navet, Jrgen Teich |
| 2015 | Potential applications based on NVM emerging technologies. | Sophiane Senni, Raphael Martins Brum, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamati, Bruno Mussard |
| 2015 | A CNN-inspired mixed signal processor based on tunnel transistors. | Behnam Sedighi, Indranil Palit, Xiaobo Sharon Hu, Joseph Nahas, Michael T. Niemier |
| 2015 | GPU-accelerated small delay fault simulation. | Eric Schneider, Stefan Holst, Michael A. Kochte, Xiaoqing Wen, Hans-Joachim Wunderlich |
| 2015 | DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS. | Michael Schaffner, Frank K. Grkaynak, Aljoscha Smolic, Luca Benini |
| 2015 | Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation. | Santanu Sarma, Nikil D. Dutt, Puneet Gupta, Nalini Venkatasubramanian, Alexandru Nicolau |
| 2015 | Online binding of applications to multiple clock domains in shared FPGA-based systems. | Farzad Samie, Lars Bauer, Chih-Ming Hsieh, Jrg Henkel |
| 2015 | Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI. | M. Saliva, Florian Cacho, Vincent Huard, X. Federspiel, D. Angot, Ahmed Benhassain, Alain Bravaix, Lorena Anghel |
| 2015 | Ageing simulation of analogue circuits and systems using adaptive transient evaluation. | Felix Salfelder, Lars Hedrich |
| 2015 | Logical equivalence checking of asynchronous circuits using commercial tools. | Arash Saifhashemi, Hsin-Ho Huang, Priyanka Bhalerao, Peter A. Beerel |
| 2015 | Design method for multiplier-less two-variable numeric function approximation. | Jochen Rust, Steffen Paul |
| 2015 | QR-decomposition architecture based on two-variable numeric function approximation. | Jochen Rust, Frank Ludwig, Steffen Paul |
| 2015 | Systematic application of ISO 26262 on a SEooC: Support by applying a systematic reuse approach. | Alejandra Ruiz, Alberto Melzi, Tim Kelly |
| 2015 | Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog cores. | Julius von Rosen, Markus Meissner, Lars Hedrich |
| 2015 | On the automatic generation of SBST test programs for in-field test. | Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker |
| 2015 | Detection of illegitimate access to JTAG via statistical learning in chip. | Xuanle Ren, Vtor Grade Tavares, R. D. (Shawn) Blanton |
| 2015 | Silicon proof of the intelligent analog IP design flow for flexible automotive components. | Torsten Reich, Benjamin Prautsch, Uwe Eichler, R. Buhl |
| 2015 | In-place memory mapping approach for optimized parallel hardware interleaver architectures. | Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy, Awais Sani |
| 2015 | Enabling multi-threaded applications on hybrid shared memory manycore architectures. | Tushar Rawat, Aviral Shrivastava |
| 2015 | DyReCTape: a <u>dy</u>namically <u>re</u>configurable <u>c</u>ache using domain wall memory <u>tape</u>s. | Ashish Ranjan, Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Vijay S. Pai, Kaushik Roy, Anand Raghunathan |
| 2015 | Worst-case communication time analysis of networks-on-chip with shared virtual channels. | Eberle A. Rambo, Rolf Ernst |
| 2015 | FPGA accelerated DNA error correction. | Anand Ramachandran, Yun Heo, Wen-mei W. Hwu, Jian Ma, Deming Chen |