| 2026 | FedCM: Fine-grained Kernel Scheduling and Management to Improve GPU Sharing. | Xianwei Zhang, Xuanteng Huang, Nong Xiao |
| 2026 | A Reusable Methodology for High-Performance Interconnects using a Standard-Cell based Asynchronous NoC Router. | Chonghui Zhang, Yizhe Hu, Yi Kang |
| 2026 | From Trigger to Impact: Knowledge-Graph Reasoning and Risk-Aware Classification for Hardware Trojan Detection. | Yang Zhang, Xing Hu, Xiaowen Chen, Huan Guo, Zhenyu Zhao, Sheng Liu |
| 2026 | Optimal Compilation of Syndrome Extraction Circuits for General Quantum LDPC Codes. | Kai Zhang, Dingchao Gao, Zhaohui Yang, Runshi Zhou, Fangming Liu, Zhengfeng Ji, Jianxin Chen |
| 2026 | A | Zhiyuan Zhang, Zhihua Fan, Wenming Li, Yudong Mu, Yuhang Qiu, Zhen Wang, Xiaochun Ye, Xuejun An |
| 2026 | Towards Trustworthy LLM-Based Assertion Generation: A Data Augmentation Framework with Formal Check Approach. | Qingchen Zhai, Hao Yu, Chen Bai, Charles Young, Frank Qu, Dezhi Ran, Yuan Xie, Tao Xie |
| 2026 | AutoShrink: Adaptive Search Space Shrinkage for Large-Scale Pareto Optimization of HLS Designs. | Yingxin Zeng, Binghao Cheng, Jianwang Zhai, Kang Zhao, Zhe Lin |
| 2026 | FSDB: A Folded-Store Dynamic-Broaden Hybrid Compute-in-ROM/SRAM Architecture for Deploying Large-Scale DNNs On-Chip. | Tianyi Yu, Teng Yi, Huazhong Yang, Xueqing Li |
| 2026 | From Buffers to Registers: Unlocking Fine-Grained FlashAttention with Hybrid-Bonded 3D NPU Co-Design. | Jinxin Yu, Yudong Pan, Mengdi Wang, Huawei Li, Yinhe Han, Xiaowei Li, Ying Wang |
| 2026 | LogHD: Robust Compression of Hyperdimensional Classifiers via Logarithmic Class-Axis Reduction. | Sanggeon Yun, Hyunwoo Oh, Ryozo Masukawa, Pietro Mercati, Nathaniel D. Bastian, Mohsen Imani |
| 2026 | DecoHD: Decomposed Hyperdimensional Classification under Extreme Memory Budgets. | Sanggeon Yun, Hyunwoo Oh, Ryozo Masukawa, Mohsen Imani |
| 2026 | Kolmogorov-Arnold Networks for Autonomous Driving: A Hardware-in-the-Loop Comparison with Conventional Deep Neural Networks. | Chaoran Yuan, Fadi J. Kurdahi |
| 2026 | Hetero-ChipletSim: Bridging Chiplet, Interconnect and Packaging Heterogeneity in Multi-Chiplet System Simulation. | Xuguang Yuan, Jiangyuan Gu, Qidie Wu, Yang Hu, Shaojun Wei, Shouyi Yin |
| 2026 | LiveVerilogEval: Contamination Free and Automatically Scalable Benchmark for Verilog Code Generation. | Charles Young, Hao Yu, Dezhi Ran, Qingchen Zhai, Tianqi Qiu, Frank Qu, Bangyan Wang, Yuan Xie, Tao Xie |
| 2026 | LUT-APP: Dynamic-Precision LUT-based Approximation Unifying Non-Linear Operations in Transformers. | Seokkyu Yoon, Namjoon Kim, Hyun Kim |
| 2026 | Breaking Standard Cell Margin Constraints for Area-Efficient VLSI Design. | Junghyun Yoon, Jooyeon Jeong, Heechun Park |
| 2026 | Boosting LLC Bandwidth Utilization in GPUs through Adaptive Fine-Grained Data Migration. | Jihun Yoon, Sungbin Jang, Seokin Hong |
| 2026 | TSIM4ICS: Trace-Driven SystemC-TLM Simulation Framework for I/O Die-Based Multi-Chiplet Systems. | Youngchul Yoon, Soonhoi Ha |
| 2026 | EMaper: Cross-level Electromigration Aware Placement and Routing EDA Workflow for Interconnects Hotspot Prediction and Mitigation. | Chenglin Ye, Yuze Lu, Yizhan Liu, Ligong Zhang, Jinghan Xu, Fei Liu, Yibo Lin, Zheng Zhou, Xiaoyan Liu |
| 2026 | AutoPMS: A Framework for Automated Power Management System Design via Hierarchical Modeling and Embedded Design Knowledge. | Bin Ye, Shuo Li |
| 2026 | Dynamic Rank-Aware Aggregation with Graph Contrastive Learning for Federated Foundation Model Fine-Tuning. | Zhao Yang, Xunyun Qiu, Hua Cui |
| 2026 | FORWORD: Accelerating Formal Datapath Verification via Word-Level Sweeping. | Ziyi Yang, Guangyu Hu, Xiaofeng Zhou, Mingkai Miao, Changyuan Yu, Wei Zhang, Hongce Zhang |
| 2026 | DARE: An Irregularity-Tolerant Matrix Processing Unit with a Densifying ISA and Filtered Runahead Execution. | Xin Yang, Xin Fan, Zengshi Wang, Jun Han |
| 2026 | Toward Parallel Serving for Vision-Language Models via Modal Decoupling and Scheduling. | Yijia Yang, Yubo Deng, Yida Wang, Yuanchao Xu, Keni Qiu |
| 2026 | SCALER: A Stream-Aware Accelerator with Hierarchical Memory for Sparse LU Factorization on HBM FPGAs. | Xin Xu, Zhiying Zhu, Zishu Li, Dan Niu, Cheng Zhuo, Zhou Jin |