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Design, Automation and Test in Europe Conference

DATE

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering · Software Engineering

Papers indexed

9,217

1995–2026

Papers per year

1995445 peak2026

DATE papers

9,217 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2025Co-Design of Sustainable Embedded Systems-on-Chip.Jan Spieck, Dominik Walter, Jan Waschkeit, Jrgen Teich
2025Decentralizing IoT Data Processing: The Rise of Blockchain-Based Solutions.Giuseppe Spadavecchia, Marco Fiore, Marina Mongiello, Daniela De Venuto
2025OpenMFDA: Microfluidic Design Automation in Three Dimensions.Ashton Snelgrove, Daniel Wakeham, Skylar Stockham, Scott Temple, Pierre-Emmanuel Gaillardon
2025Improving Software Reliability with Rust: Implementation for Enhanced Control Flow Checking Methods.Jacopo Sini, Mohammadreza Amel Solouki, Massimo Violante, Giorgio Di Natale
2025SAFELOC: Overcoming Data Poisoning Attacks in Heterogeneous Federated Machine Learning for Indoor Localization.Akhil Singampalli, Danish Gufran, Sudeep Pasricha
2025Multi-Partner Project: Architectures and Design Methodologies to Accelerate AI Workloads. The ICSC Flagship 2 Project.Cristina Silvano, Fabrizio Ferrandi, Serena Curzel, Daniele Ielmini, Stefania Perri, Fanny Spagnolo, Pasquale Corsonello, Sebastiano Fabio Schifano, Cristian Zambelli, Angelo Garofalo, Francesco Conti, Luca Benini
2025Timing-Driven Global Placement by Efficient Critical Path Extraction.Yunqi Shi, Siyuan Xu, Shixiong Kai, Xi Lin, Ke Xue, Mingxuan Yuan, Chao Qian
2025SparseInfer: Training-free Prediction of Activation Sparsity for Fast LLM Inference.Jiho Shin, Hoeseok Yang, Youngmin Yi
2025FlexENM: A Flexible Encrypting-Near-Memory with Refresh-Less eDRAM-Based Multi-Mode AES.Hyunseob Shin, Jaeha Kung
2025Handling Latch Loops in Timing Analysis with Improved Complexity and Divergent Loop Detection.Xizhe Shi, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang
2025Joint DNN Partition and Thread Allocation Optimization for Energy-Harvesting MEC Systems.Yizhou Shi, Liying Li, Yue Zeng, Peijin Cong, Junlong Zhou
2025TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs.Diyou Shen, Yichao Zhang, Marco Bertuletti, Luca Benini
2025INTO-OA: Interpretable Topology Optimization for Operational Amplifiers.Jinyi Shen, Fan Yang, Li Shang, Zhaori Bi, Changhao Yan, Dian Zhou, Xuan Zeng
2025A Resource-Aware Residual-Based Gaussian Belief Propagation Accelerator Toolflow.Omar Sharif, Christos-Savvas Bouganis
2025SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis.Kunming Shao, Fengshi Tian, Xiaomeng Wang, Jiakun Zheng, Jia Chen, Jingyu He, Hui Wu, Jinbo Chen, Xihao Guan, Yi Deng, Fengbin Tu, Jie Yang, Mohamad Sawan, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui
2025AIRCHITECT v2: Learning the Hardware Accelerator Design Space Through Unified Representations.Jamin Seo, Akshat Ramachandran, Yu-Chuan Chuang, Anirudh Itagi, Tushar Krishna
2025Deterministic Fault-Tolerant State Preparation for Near-Term Quantum Error Correction: Automatic Synthesis Using Boolean Satisfiability.Ludwig Schmid, Tom Peham, Lucas Berent, Markus Mller, Robert Wille
2025Fast Interpreter-Based Instruction Set Simulation for Virtual Prototypes.Manfred Schlgl, Daniel Groe
2025Hardware/Software Runtime for GPSA Protection in RISC-V Embedded Cores.Louis Savary, Simon Rokicki, Steven Derrien
2025HiFi-SAGE: High Fidelity GraphSAGE-Based Latency Estimators for DNN Optimization.Shambhavi Balamuthu Sampath, Leon Hecht, Moritz Thoma, Lukas Frickenstein, Pierpaolo Mor, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone
2025Signal Prediction for Digital Circuits by Sigmoidal Approximations Using Neural Networks.Josef Salzmann, Ulrich Schmid
2025EGIS: Entropy Guided Image Synthesis for Dataset-Agnostic Testing of RRAM-Based DNNs.Anurup Saha, Chandramouli N. Amarnath, Kwondo Ma, Abhijit Chatterjee
2025BIMAX: A Bitwise In-Memory Accelerator Using 6T-SRAM Structure.Nezam Rohbani, Mohammad Arman Soleimani, Behzad Salami, Osman S. Unsal, Adrin Cristal Kestelman, Hamid Sarbazi-Azad
2025RVEBS: Event-Based Sampling on RISC-V.Tiago Rocha, Nuno Neves, Nuno Roma, Pedro Toms, Leonel Sousa
2025SimGen: Simulation Pattern Generation for Efficient Equivalence Checking.Carmine Rizzi, Sarah Brunner, Alan Mishchenko, Lana Josipovic
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