| 2014 | A Field Programmable Gate Array-Based Digital Temperature Sensor with Improved Immunity to Static Supply Shift. | Princewill Akpojotor, Ayodeji Oluwatope, Kayode Ayodele, G. Adesola Aderounmu, Emmanuel Rotimi Adagunodo |
| 2014 | An Elliptic Curve Crypto-Processor Secured by Randomized Windows. | Simon Pontie, Paolo Maistri, Rgis Leveugle |
| 2014 | The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications. | Jakub Podivinsky, Ondrej Cekan, Marcela Simkov, Zdenek Kotsek |
| 2014 | P-SOCRATES: A Parallel Software Framework for Time-Critical Many-Core Systems. | Lus Miguel Pinho, Eduardo Quiones, Marko Bertogna, Andrea Marongiu, Jorge Pereira Carlos, Claudio Scordino, Michele Ramponi |
| 2014 | Design of Fault-Secure Transposed FIR Filters Protected Using Residue Codes. | Stanislaw J. Piestrak, Piotr Patronik |
| 2014 | A Safety Certification Strategy for IEC-61508 Compliant Industrial Mixed-Criticality Systems Based on Multicore Partitioning. | Jon Prez, David Gonzlez, Carlos Fernando Nicols, Ton Trapman, Jose Miguel Garate |
| 2014 | End-to-End Real-Time Communication in Mixed-Criticality Systems Based on Networked Multicore Chips. | Roman Obermaisser, Zaher Owda, Mohammed Abuteir, Hamidreza Ahmadian, Donatus Weber |
| 2014 | Closing the Gap between Speed and Configurability of Multi-bit Fault Emulation Environments for Security and Safety-Critical Designs. | Ralph Nyberg, Jrgen Nolles, Johann Heyszl, Dirk Rabe, Georg Sigl |
| 2014 | Automatic Synthesis over Multiple APIs from Uml/Marte Models for Easy Platform Mapping and Reuse. | Alejandro Nicols, Pablo Peil, Hctor Posadas, Eugenio Villar |
| 2014 | Iterative FPGA Implementation Easing Safety Certification for Mixed-Criticality Embedded Real-Time Systems. | Daniel Mnch, Michael Paulitsch, Michael Honold, Wolfgang Schlecker, Andreas Herkersdorf |
| 2014 | Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates. | Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2014 | Development Framework for Model Driven Architecture to Accomplish Power-Aware Embedded Systems. | Manuel Menghin, Norbert Druml, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid |
| 2014 | Automatic Construction of On-line Checking Circuits Based on Finite Automata. | Lucie Matuova, Jan Kastil, Zdenek Kotsek |
| 2014 | Towards Component-Based Design of Safety-Critical Cyber-Physical Applications. | Alejandro Masrur, Michal Kit, Toms Bures, Wolfram Hardt |
| 2014 | Prospeckz-5 - A Wireless Sensor Platform for Tracking and Monitoring of Wild Horses. | Janek Mann, Ion Emilian Radoi, D. K. Arvind |
| 2014 | Anytime System Level Verification via Random Exhaustive Hardware in the Loop Simulation. | Toni Mancini, Federico Mari, Annalisa Massini, Igor Melatti, Enrico Tronci |
| 2014 | Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA. | Mahdi Jelodari Mamaghani, Jim D. Garside, William B. Toms, Doug A. Edwards |
| 2014 | Design of a Redundant FPGA-Based Safety System for Railroad Vehicles. | David Macii, Manuel Avancini, Luigi Benciolini, Stefano Dalpez, Michele Corr, Roberto Passerone |
| 2014 | Minimizing Reversible Circuits in the 2n Scheme Using Two and Three Bits Patterns. | Martin Lukac, Maher Hawash, Michitaka Kameyama, Marek A. Perkowski, Pawel Kerntopf |
| 2014 | Data-and State-Dependent Power Characterisation and Simulation of Black-Box RTL IP Components at System Level. | Daniel Lorenz, Kim Grttner, Wolfgang Nebel |
| 2014 | Simulation Alternatives for Modeling Networked Cyber-Physical Systems. | Michele Lora, Riccardo Muradore, Riccardo Reffato, Franco Fummi |
| 2014 | Accelerating Volume Image Registration through Correlation Ratio Based Methods on GPUs. | Ang Li, Akash Kumar |
| 2014 | Three-Dimensional Design Space Exploration for System Level Synthesis. | Shuo Li, Ahmed Hemani |
| 2014 | A Fault Attack Emulation Environment to Evaluate Java Card Virtual-Machine Security. | Michael Lackner, Reinhard Berlach, Michael Hraschan, Reinhold Weiss, Christian Steger |
| 2014 | NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes. | Halil Kukner, Pieter Weckx, Sebastien Morrison, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, Guido Groeseneken |