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Euromicro Conference Series on Digital System Design

DSD

C

CORE rank

CORE rank (raw)

C

Fields of research

Computer Systems Engineering · Distributed Computing and Systems Software

Papers indexed

2,448

2001–2025

Papers per year

2001136 peak2025

DSD papers

2,448 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2009A Concept for Logic Self Repair.Tobias Koal, Heinrich Theodor Vierhaus, Daniel Scheit
2009Reliability Estimation Process.Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus
2009Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology.George Kiokes, George Economakos, Angelos Amditis, Nikolaos K. Uzunoglu
2009Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing.Jan Kastil, Jan Korenek, Ondrej Lengl
2009Stereo Vision Algorithm Implementation in FPGA Using Census Transform for Effective Resource Optimization.Mario Alberto Ibarra-Manzano, Dora Luz Almanza-Ojeda, Michel Devy, Jean-Louis Boizard, Jean-Yves Fourniols
2009Pulse Generation for On-chip Data Transmission.Simon Hollis
2009Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment.Zhiyuan He, Zebo Peng, Petru Eles
2009A MPSoC Prototyping Platform for Flexible Radio Applications.Damien Hedde, Pierre-Henri Horrein, Frdric Ptrot, Robin Rolland, Franck Rousseau
2009High Reliable Remote Terminal Unit for Space Applications.David Guzmn, Manuel Prieto, Daniel Garcia, Victor Ruiz, Javier Almena, Sebastin Snchez-Prieto, Daniel Meziat
2009Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study.Alexandre Guerre, Nicolas Ventroux, Raphal David, Alain Mrigot
2009Internet-Router Buffered Crossbars Based on Networks on Chip.Kees Goossens, Lotfi Mhamdi, Iria Varela Senin
2009Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture.Marius Gligor, Nicolas Fournel, Frdric Ptrot
2009Streaming Reduction Circuit.Marco Gerards, Jan Kuper, Andr B. J. Kokkeler, Bert Molenkamp
2009Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications.Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi, Javier Sosa, Hctor Navarro
2009High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic.Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi
2009High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V Output.Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi
2009Acceleration of MELP Algorithm Using DSP Coprocessor with Extended Registers.Lu Gao, Li Guo, Canxing Lu
2009Time-Varying Network Fault Model for the Design of Dependable Networked Embedded Systems.Franco Fummi, Davide Quaglia, Francesco Stefanni
2009Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic.Werner Friesenbichler, Andreas Steininger
2009Robustness Check for Multiple Faults Using Formal Techniques.Stefan Frehse, Grschwin Fey, Andr Slflow, Rolf Drechsler
2009One Dimensional Systolic Inversion Architecture Based on Modified GF(2^k) Extended Euclidean Algorithm.Apostolos P. Fournaris, Odysseas G. Koufopavlou
2009An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload.Pierfrancesco Foglia, Francesco Panicucci, Cosimo Antonio Prete, Marco Solinas
2009A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms.Petr Fiser, David Toman
2009Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation.Daniel Piso Fernandez, Javier D. Bruguera
2009A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling.Mohammad Fattah, Soodeh Aghli Moghaddam, Siamak Mohammadi
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