| 2009 | Iterative Algorithm for Compound Instruction Selection with Register Coalescing. | Minwook Ahn, Jonghee M. Youn, Youngkyu Choi, Doosan Cho, Yunheung Paek |
| 2009 | Low-Power Low-Energy Prime-Field ECC Processor Based on Montgomery Modular Inverse Algorithm. | Hamid Reza Ahmadi, Ali Afzali-Kusha |
| 2009 | A Standardized Knobs and Monitors RTL2RTL Insertion Methodology for Fine Grain SoC Tuning. | Ahmed Mohamed AbdelHamid, Ankur Anchlia, Stylianos Mamagkakis, Miguel Corbalan Miranda, Bart Dierickx, Maarten Kuijk |
| 2009 | Model-Driven Design of Embedded Multimedia Applications on SoCs. | Adolf Samir Abdallah, Abdoulaye Gamati, Jean-Luc Dekeyser |
| 2008 | Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations. | Sharareh Zamanzadeh, Mohammad Mirza-Aghatabar, Mehrdad Najibi, Hossein Pedram, Abolghasem Sadeghi |
| 2008 | An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty. | Morteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi |
| 2008 | Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration. | Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, Jos L. Nez-Yez |
| 2008 | Improving SER Immunity of Combinational Logic Using Combinations of Spatial and Temporal Checking. | Tsau-Shuan Wu, Alkan Cengiz, Tom W. Chen |
| 2008 | Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. | Christophe Wolinski, Krzysztof Kuchcinski, Jrgen Teich, Frank Hannig |
| 2008 | A Network-on-Chip Channel Allocator for Run-Time Task Scheduling in Multi-Processor System-on-Chips. | Markus Winter, Gerhard P. Fettweis |
| 2008 | Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. | Robert Wille, Grschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler |
| 2008 | Embedded Diagnostic Logic Test Exploiting Regularity. | Heinrich Theodor Vierhaus, Ren Kothe |
| 2008 | On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. | Haridimos T. Vergos, Dimitris Bakalis |
| 2008 | Design of a Two Dimensional PRSI Image Processor. | Theja Tulabandhula, Amit Patra, Nirmal B. Chakrabarti |
| 2008 | Implementation of Self-Timed Circuits onto FPGAs Using Commercial Tools. | Maurizio Tranchero, Leonardo Maria Reyneri |
| 2008 | CART: Communication-Aware Routing Technique for Application-Specific NoCs. | Rafael Tornero, Juan Manuel Ordua, Andres Mejia, Jos Flich, Jos Duato |
| 2008 | Pearson - based Analysis of Positioning Error Distribution in Wireless Sensor Networks. | Stefano Tennina, Marco Di Renzo, Fabio Graziosi, Fortunato Santucci |
| 2008 | TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path. | Josef Strnadel |
| 2008 | Digital Systems Architectures Based on On-line Checkers. | Martin Straka, Zdenek Kotsek, Jan Winter |
| 2008 | An Analysis of Connectivity and Yield for 2D Mesh Based NoC with Interconnect Router Failures. | Thomas Sdring, shild Grnstad Solheim, Tor Skeie, Sven-Arne Reinemo |
| 2008 | Power Conscious RTL Test Scheduling. | Jaroslav Skarvada, Zdenek Kotsek, Tomas Herrman |
| 2008 | A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures. | Magnus Sjlander, Andrei Sergeevich Terechko, Marc Duranton |
| 2008 | Design of a Distributed Embedded System for Domotic Applications. | Francesco Sechi, Luca Fanucci, Stefano Luschi, Simone Perini, Matteo Madesani |
| 2008 | A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching. | Simone Secchi, Francesca Palumbo, Danilo Pani, Luigi Raffo |
| 2008 | Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units. | Nuno Sebastio, Tiago Dias, Nuno Roma, Paulo F. Flores, Leonel Sousa |