| 2001 | Fast Test Cost Calculation for Hybrid BIST in Digital Systems. | Elmet Orasson, Rein Raidma, Raimund Ubar, Gert Jervan, Zebo Peng |
| 2001 | Synchronizing Low-Cost Energy Aware Sensors in a Short-range Wireless Cell. | Mikael M. Nordman, Wojciech E. Kozlowski, Olavi Vhmki |
| 2001 | Improving Single-Thread Fetch Performance on a Multithreaded Processor. | Juan C. Moure, R. B. Garca, Dolores Rexachs, Emilio Luque |
| 2001 | A Multiple Context Reconfigurable Functional Unit. | Michael C. Miller, Daniel Tabak |
| 2001 | On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. | Enrique San Milln, Luis Entrena, Jos Alberto Espejo |
| 2001 | Traffic Scheduling Coprocessor with Schedulability Analysis Capability. | Ernesto Martins, Jos Alberto Fonseca |
| 2001 | A Wireless Interconnection Network for Parallel Processing. | Jacek Marczynski, Daniel Tabak |
| 2001 | Synchronizing a High-Speed SIMD Processor Array. | Stefan Lund, Lars Bengtsson |
| 2001 | High-Performance Floating Point Divide. | Albert A. Liddicoat, Michael J. Flynn |
| 2001 | Synthesis of ASM-based Self-Checking Controllers. | Ilya Levin, Vladimir Sinelnikov, Mark G. Karpovsky |
| 2001 | Test Strategies on Functionally Partitioned Module-Based Programmable Architecture for Base-Band Processing. | Simon Leung, Adam Postula, Ahmed Hemani |
| 2001 | A MIMD-Based Multi Threaded Real-Time Processor for Pattern Recognition. | F. Lesser, Jan de Cuveland, Volker Lindenstruth, C. Reichling, R. Schneider, M. W. Schulz |
| 2001 | Synthesis of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs and Constraint Logic Programming. | Krzysztof Kuchcinski, Christophe Wolinski |
| 2001 | Adaptability, Extensibility, and Flexibility in Real-Time Operating Systems. | Pramote Kuacharoen, Tankut Akgul, Vincent John Mooney, Vijay K. Madisetti |
| 2001 | A HW/SW Codesign Framework Based on Distributed DSP Virtual Machines. | Christian Kreiner, Christian Steger, Egon Teiniker, Reinhold Weiss |
| 2001 | Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing. | Andrzej Krasniewski |
| 2001 | Very High (Over 40 Gb/s) Speed Circuits for Optical Communications - Design Methodolgy and Application Examples. | Agnieszka Konczykowska |
| 2001 | Two-Criterial Constraint-Driven FSM State Encoding for Low Power. | Manfred Koegst, Steffen Rlke, Gnter Franke, Maria J. Avedillo |
| 2001 | An Approach to Minimization of Decision Diagrams . | Pawel Kerntopf |
| 2001 | Timing Driven Wiring on an Advanced Microprocessor. | Paul Kartschoke, Stephen F. Geissler |
| 2001 | Minimization of OPKFDDs Using Genetic Algorithms. | Migyoung Jung, Gueesang Lee, Sungju Park, Rolf Drechsler |
| 2001 | Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis. | Lech Jzwiak, Artur Chojnacki, Aleksander Slusarczyk |
| 2001 | Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures. | Lech Jzwiak, Artur Chojnacki |
| 2001 | Genetic Programming in FPGA Implementation of Addition as a Part of the Convolution. | Ernest Jamro, Kazimierz Wiatr |
| 2001 | FPGA Implementation of Addition as a Part of the Convolution. | Ernest Jamro, Kazimierz Wiatr |