| 2015 | Design and simulation tools for Embedded NOCs on FPGAs. | Mohamed S. Abdelfattah, Andrew Bitar, Ange Yaghi, Vaughn Betz |
| 2015 | Software-in-the-Loop simulation of embedded control applications based on Virtual Platforms. | Stephan Werner, Leonard Masing, Fabian Lesniak, Jrgen Becker |
| 2014 | High-precision self-characterization for the LUT burn-in information leakage threat. | Kenneth M. Zick, Sen Li, Matthew French |
| 2014 | A secure and unclonable embedded system using instruction-level PUF authentication. | Jason Xin Zheng, Dongfang Li, Miodrag Potkonjak |
| 2014 | A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. | Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi |
| 2014 | Patra: Parallel tree-reweighted message passing architecture. | Wenlai Zhao, Haohuan Fu, Guangwen Yang, Wayne Luk |
| 2014 | A semi-supervised modeling approach for performance characterization of FPGA architectures. | Liqun Yang, Haigang Yang, Wei Li, Zhihua Li, Zhihong Huang, Colin Yu Lin |
| 2014 | Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor. | Chen Yang, Leibo Liu, Yansheng Wang, Shouyi Yin, Peng Cao, Shaojun Wei |
| 2014 | Particle filtering-based Maximum Likelihood Estimation for financial parameter estimation. | Jinzhe Yang, Binghuan Lin, Wayne Luk, Terence Nahar |
| 2014 | RAM-based hardware accelerator for network data anonymization. | Fumito Yamaguchi, Kanae Matsui, Hiroaki Nishi |
| 2014 | Robust and flexible FPGA-based digital PUF. | Teng Xu, Miodrag Potkonjak |
| 2014 | Privacy preserving large scale DNA read-mapping in MapReduce framework using FPGAs. | Lei Xu, Han-Yee Kim, Xi Wang, Weidong Shi, Taeweon Suh |
| 2014 | FPGA implementation of a multi-algorithm parallel FEC for SDR platforms. | Zhenzhi Wu, Dake Liu, Zheng Yang, Qingying Wang, Wei Zhou |
| 2014 | Efficient 3D triangulation in hardware for dense structure-from-motion in low-speed automotive scenarios. | Stefan Wonneberger, Max Kohler, Wojciech Derendarz, Thorsten Graf, Rolf Ernst |
| 2014 | Enabling SRAM-PUFs on Xilinx FPGAs. | Alexander Wild, Tim Gneysu |
| 2014 | Using high-level knowledge to enhance data channels in FPGA streaming systems. | Marlon Wijeyasinghe, David Thomas |
| 2014 | Leakage and performance aware resource management for 2D dynamically reconfigurable FPGA architectures. | Siqi Wang, Pham Nam Khanh, Amit Kumar Singh, Akash Kumar |
| 2014 | DyRACT: A partial reconfiguration enabled accelerator and test platform. | Kizheppatt Vipin, Suhaib A. Fahmy |
| 2014 | Fast and accurate SEU-tolerance characterization method for Zynq SoCs. | Igor Villata, Unai Bidarte, Uli Kretzschmar, Armando Astarloa, Jess Lzaro |
| 2014 | Trends of CPU, GPU and FPGA for high-performance computing. | Mrio P. Vstias, Horcio C. Neto |
| 2014 | Multi-directional error correction schemes for SRAM-based FPGAs. | Shyamsundar Venkataraman, Rui Santos, Sidharth Maheshwari, Akash Kumar |
| 2014 | A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs. | Shyamsundar Venkataraman, Rui Santos, Anup Das, Akash Kumar |
| 2014 | Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use. | Jasmina Vasiljevic, Paul Chow |
| 2014 | A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. | Juan Valverde, Alfonso Rodrguez, Julio Camarero, Andrs Otero, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo |
| 2014 | Pattern-based FPGA logic block and clustering algorithm. | Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |