| 1993 | Piecewise linear models for Rsim. | Russell Kao, Mark Horowitz |
| 1993 | Test generation for multiple faults based on parallel vector pair analysis. | Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita |
| 1993 | High throughput pipelined data path synthesis by conserving the regularity of nested loops. | Yuan-Long Jeang, Yu-Chin Hsu, Jhing-Fa Wang, Jau-Yien Lee |
| 1993 | A grid-based approach for connectivity binding with geometric costs. | Hyuk-Jae Jang, Barry M. Pangrle |
| 1993 | Inverter minimization in multi-level logic networks. | Alok Jain, Randal E. Bryant |
| 1993 | Retiming gated-clocks and precharged circuit structures. | Alexander T. Ishii |
| 1993 | Practical applications of an efficient time separation of events algorithm. | Henrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello |
| 1993 | Scheduling a minimum dependence in FSMs. | Steve C.-Y. Huang, Wayne H. Wolf |
| 1993 | Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors. | Ing-Jer Huang, Alvin M. Despain |
| 1993 | An improved method for RTL synthesis with testability tradeoffs. | Haidar Harmanani, Christos A. Papachristou |
| 1993 | A symbolic algorithm for maximum flow in 0-1 networks. | Gary D. Hachtel, Fabio Somenzi |
| 1993 | Representation and symbolic manipulation of linearly inductive Boolean functions. | Aarti Gupta, Allan L. Fisher |
| 1993 | High level synthesis for reconfigurable datapath structures. | Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey |
| 1993 | A visual design environment. | Eric J. Golin, Annette C. Feng, Linus Huang, Eric Hughes |
| 1993 | Quadratic zero-one programming based synthesis of application specific data paths. | Werner Geurts, Francky Catthoor, Hugo De Man |
| 1993 | Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures. | Arjan J. van Genderen, N. P. van der Meijs |
| 1993 | Minimum crosstalk channel routing. | Tong Gao, C. L. Liu |
| 1993 | Test quality and yield analysis using the DEFAM defect to fault mapper. | Dinesh D. Gaitonde, Duncan M. Hank Walker |
| 1993 | Interleaving based variable ordering methods for ordered binary decision diagrams. | Hiroshige Fujii, Goichi Ootomo, Chikahiro Hori |
| 1993 | Sequential logic optimization by redundancy addition and removal. | Luis Entrena, Kwang-Ting Cheng |
| 1993 | State look ahead technique for cycle optimization of interacting finite state Moore machines. | Wolfgang Ecker, Michael Hofmeister |
| 1993 | New faster Kernighan-Lin-type graph-partitioning algorithms. | Shantanu Dutt |
| 1993 | Exploiting hardware sharing in high-level synthesis for partial scan optimization. | Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy |
| 1993 | Event driven adaptively controlled explicit simulation of integrated circuits. | Anirudh Devgan, Ronald A. Rohrer |
| 1993 | Efficient modeling of switch-level networks containing undetermined logic node states. | Peter Dahlgren, Peter Lidn |