| 2017 | Fault injection attack on deep neural network. | Yannan Liu, Lingxiao Wei, Bo Luo, Qiang Xu |
| 2017 | MT-spike: A multilayer time-based spiking neuromorphic architecture with temporal error backpropagation. | Tao Liu, Zihao Liu, Fuhong Lin, Yier Jin, Gang Quan, Wujie Wen |
| 2017 | VST: A virtual stress testing framework for discovering bugs in SSD flash-translation layers. | Ren-Shuo Liu, Yun-Sheng Chang, Chih-Wen Hung |
| 2017 | Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs. | Tengtao Li, Sachin S. Sapatnekar |
| 2017 | Redistribution layer routing for wafer-level integrated fan-out package-on-packages. | Ting-Chou Lin, Chia-Chih Chi, Yao-Wen Chang |
| 2017 | UTPlaceF 3.0: A parallelization framework for modern FPGA global placement: (Invited paper). | Wuxi Li, Meng Li, Jiajun Wang, David Z. Pan |
| 2017 | CNN-based pattern recognition on nonvolatile IoT platform for smart ultraviolet monitoring: (Invited paper). | Jinyang Li, Qingwei Guo, Fang Su, Zhe Yuan, Jinshan Yue, Jingtong Hu, Huazhong Yang, Yongpan Liu |
| 2017 | Energy-efficient, high-performance, highly-compressed deep neural network design using block-circulant matrices. | Siyu Liao, Zhe Li, Xue Lin, Qinru Qiu, Yanzhi Wang, Bo Yuan |
| 2017 | Sequential engineering change order under retiming and resynthesis. | Nian-Ze Lee, Victor N. Kravets, Jie-Hong R. Jiang |
| 2017 | A streaming clustering approach using a heterogeneous system for big data analysis. | Dajung Lee, Alric Althoff, Dustin Richmond, Ryan Kastner |
| 2017 | Clock-aware placement for large-scale heterogeneous FPGAs. | Yun-Chih Kuo, Chau-Chin Huang, Shih-Chun Chen, Chun-Han Chiang, Yao-Wen Chang, Sy-Yen Kuo |
| 2017 | Efficient simulation of EM side-channel attack resilience. | Amit Kumar, Cody Scarborough, Ali E. Yilmaz, Michael Orshansky |
| 2017 | Data path optimisation and delay matching for asynchronous bundled-data balsa circuits. | Norman Kluge, Ralf Wollowski |
| 2017 | P | Yeseong Kim, Pietro Mercati, Ankit More, Emily Shriver, Tajana Rosing |
| 2017 | ORCHARD: Visual object recognition accelerator based on approximate in-memory processing. | Yeseong Kim, Mohsen Imani, Tajana Rosing |
| 2017 | Overview of the 2017 CAD contest at ICCAD: Invited paper. | Myung-Chul Kim, Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake |
| 2017 | Threshold-based obfuscated keys with quantifiable security against invasive readout. | Shahrzad Keshavarz, Daniel E. Holcomb |
| 2017 | A case for low frequency single cycle multi hop NoCs for energy efficiency and high performance. | Monodeep Kar, Tushar Krishna |
| 2017 | DATC RDF: Robust design flow database: Invited paper. | Jinwook Jung, Pei-Yu Lee, Yan-Shiun Wu, Nima Karimpour Darav, Iris Hui-Ru Jiang, Victor N. Kravets, Laleh Behjat, Yih-Lang Li, Gi-Joon Nam |
| 2017 | An assessment of vulnerability of hardware neural networks to dynamic voltage and temperature variations. | Xun Jiao, Mulong Luo, Jeng-Hau Lin, Rajesh K. Gupta |
| 2017 | Dependable integrated clinical system architecture with runtime verification. | Yu Jiang, Mingzhe Wang, Han Liu, Mohammad Hosseini, Jiaguang Sun |
| 2017 | A novel cache bank timing attack. | Zhen Hang Jiang, Yunsi Fei |
| 2017 | Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations. | Adam M. Izraelevitz, Jack Koenig, Patrick Li, Richard Lin, Angie Wang, Albert Magyar, Donggyu Kim, Colin Schmidt, Chick Markley, Jim Lawson, Jonathan Bachrach |
| 2017 | Sortex: Efficient timing-driven synthesis of reconfigurable flow-based biochips for scalable single-cell screening. | Mohamed Ibrahim, Aditya Sridhar, Krishnendu Chakrabarty, Ulf Schlichtmann |
| 2017 | Why you should care about don't cares: Exploiting internal don't care conditions for hardware Trojans. | Wei Hu, Lu Zhang, Armaiti Ardeshiricham, Jeremy Blackstone, Bochuan Hou, Yu Tai, Ryan Kastner |