| 2016 | Architectural-space exploration of approximate multipliers. | Semeen Rehman, Walaa El-Harouni, Muhammad Shafique, Akash Kumar, Jrg Henkel |
| 2016 | Multilevel design understanding: from specification to logic (invited paper). | Sandip Ray, Ian G. Harris, Grschwin Fey, Mathias Soeken |
| 2016 | BoostNoC: power efficient network-on-chip architecture for near threshold computing. | Chidhambaranathan Rajamanikkam, Rajesh J. S., Koushik Chakraborty, Sanghamitra Roy |
| 2016 | RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs. | Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu |
| 2016 | Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. | Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne |
| 2016 | Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip. | Andrea Peano, Luca Ramini, Marco Gavanelli, Maddalena Nonato, Davide Bertozzi |
| 2016 | GPlace: a congestion-aware placement tool for ultrascale FPGAs. | Ryan Pattison, Ziad Abuowaimer, Shawki Areibi, Gary Grwal, Anthony Vannelli |
| 2016 | Design space exploration of drone infrastructure for large-scale delivery services. | Sangyoung Park, Licong Zhang, Samarjit Chakraborty |
| 2016 | Scope - quality retaining display rendering workload scaling based on user-smartphone distance. | Kent W. Nixon, Xiang Chen, Yiran Chen |
| 2016 | A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops. | Giuseppe Natale, Giulio Stramondo, Pietro Bressana, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio |
| 2016 | The art of semi-formal bug hunting. | Pradeep Kumar Nalla, Raj Kumar Gajavelly, Jason Baumgartner, Hari Mony, Robert Kanzelman, Alexander Ivrii |
| 2016 | Statistical methodology to identify optimal placement of on-chip process monitors for predicting fmax. | Szu-Pang Mu, Wen-Hsiang Chang, Mango C.-T. Chao, Yi-Ming Wang, Ming-Tung Chang, Min-Hsiu Tsai |
| 2016 | Design of power-efficient approximate multipliers for approximate artificial neural networks. | Vojtech Mrazek, Syed Shakib Sarwar, Luks Sekanina, Zdenek Vascek, Kaushik Roy |
| 2016 | Efficient synthesis of graph methods: a dynamically scheduled architecture. | Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Marco Lattuada, Fabrizio Ferrandi |
| 2016 | LRR-DPUF: learning resilient and reliable digital physical unclonable function. | Jin Miao, Meng Li, Subhendu Roy, Bei Yu |
| 2016 | Critical path isolation for time-to-failure extension and lower voltage operation. | Yutaka Masuda, Masanori Hashimoto, Takao Onoye |
| 2016 | BugMD: automatic mismatch diagnosis for bug triaging. | Biruk Mammo, Milind Furia, Valeria Bertacco, Scott A. Mahlke, Daya Shanker Khudia |
| 2016 | Are proximity attacks a threat to the security of split manufacturing of integrated circuits? | Jonathon Magaa, Daohang Shi, Azadeh Davoodi |
| 2016 | A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel. | Sicheng Li, Yandan Wang, Wujie Wen, Yu Wang, Yiran Chen, Hai Li |
| 2016 | An optimization-theoretic approach for attacking physical unclonable functions. | Yuntao Liu, Yang Xie, Chongxi Bao, Ankur Srivastava |
| 2016 | Provably secure camouflaging strategy for IC protection. | Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, David Z. Pan |
| 2016 | Control synthesis and delay sensor deployment for efficient ASV designs. | Chaofan Li, Sachin S. Sapatnekar, Jiang Hu |
| 2016 | MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes. | Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan |
| 2016 | Redistribution layer routing for integrated fan-out wafer-level chip-scale packages. | Bo-Qiao Lin, Ting-Chou Lin, Yao-Wen Chang |
| 2016 | SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICs. | Jai-Ming Lin, Po-Yang Chiu, Yen-Fu Chang |