| 2013 | Improved SAT-based ATPG: more constraints, better compaction. | Stephan Eggersgl, Robert Wille, Rolf Drechsler |
| 2013 | Aging-aware logic synthesis. | Mojtaba Ebrahimi, Fabian Oboril, Saman Kiamehr, Mehdi Baradaran Tahoori |
| 2013 | Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library. | Yuelin Du, Daifeng Guo, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang, Qiang Ma |
| 2013 | Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis. | Nagu R. Dhanwada, David J. Hathaway, Victor V. Zyuban, Peng Peng, Karl Moody, William W. Dungan, Arun Joseph, Rahul M. Rao, Christopher J. Gonzalez |
| 2013 | Simulation of temporal stochastic phenomena in electronic and biological systems: a comparative review, examples and synergies. | Alper Demir, Burak Erman |
| 2013 | BAG: a designer-oriented integrated framework for the development of AMS circuit generators. | John Crossley, Alberto Puggelli, Hanh-Phuc Le, B. Yang, R. Nancollas, Kwangmo Jung, Lingkai Kong, Nathan Narevsky, Yue Lu, Nicholas Sutardja, E. J. An, Alberto L. Sangiovanni-Vincentelli, Elad Alon |
| 2013 | Automatic concolic test generation with virtual prototypes for post-silicon validation. | Kai Cong, Fei Xie, Li Lei |
| 2013 | Optimization of interconnects between accelerators and shared memories in dark silicon. | Jason Cong, Bingjun Xiao |
| 2013 | LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs. | Minsik Cho, Hua Xiang, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri |
| 2013 | Conquering the scheduling alternative explosion problem of SystemC symbolic simulation. | Chun-Nan Chou, Chen-Kai Chu, Chung-Yang (Ric) Huang |
| 2013 | Efficient analog layout prototyping by layout reuse with routing preservation. | Ching-Yu Chin, Po-Cheng Pan, Hung-Ming Chen, Tung-Chieh Chen, Jou-Chun Lin |
| 2013 | A just-in-time customizable processor. | Liang Chen, Joseph Tarango, Tulika Mitra, Philip Brisk |
| 2013 | A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoring. | Qiuwen Chen, Qinru Qiu, Hai Li, Qing Wu |
| 2013 | Dynamic server power capping for enabling data center participation in power markets. | Hao Chen, Can Hankendi, Michael C. Caramanis, Ayse K. Coskun |
| 2013 | Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms. | Debapriya Chatterjee, Biruk Mammo, Doowon Lee, Raviv Gal, Ronny Morad, Amir Nahir, Avi Ziv, Valeria Bertacco |
| 2013 | Redundancy-aware electromigration checking for mesh power grids. | Sandeep Chatterjee, Mohammad Fawaz, Farid N. Najm |
| 2013 | Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os. | Daniel W. Chang, Young Hoon Son, Jung Ho Ahn, Hoyoung Kim, Minwook Ahn, Michael J. Schulte, Nam Sung Kim |
| 2013 | A disturb-alleviation scheme for 3D flash memory. | Yu-Ming Chang, Yuan-Hao Chang, Tei-Wei Kuo, Hsiang-Pang Li, Yung-Chun Li |
| 2013 | PROTON: an automatic place-and-route tool for optical networks-on-chip. | Anja Boos, Luca Ramini, Ulf Schlichtmann, Davide Bertozzi |
| 2013 | DREAMS: DFM rule EvAluation using manufactured silicon. | Ronald D. Blanton, Fa Wang, Cheng Xue, Pranab K. Nag, Yang Xue, Xin Li |
| 2013 | FPGA simulation engine for customized construction of neural microcircuits. | Hugh T. Blair, Jason Cong, Di Wu |
| 2013 | Unleashing the potential of MLC STT-RAM caches. | Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li |
| 2013 | ISOMER: integrated selection, partitioning, and placement methodology for reconfigurable architectures. | Rana Muhammad Bilal, Rehan Hafiz, Muhammad Shafique, Saad Shoaib, Asim Munawar, Jrg Henkel |
| 2013 | Techniques and challenges of implementing large scale logic design models in massively parallel fine-grained multiprocessor systems. | Platon Beletsky, Michael Bershteyn, Alexandre Birguer, Chunkuen Ho, Viktor Salitrennik |
| 2013 | ICCAD-2013 CAD contest in mask optimization and benchmark suite. | Shayak Banerjee, Zhuo Li, Sani R. Nassif |