| 1999 | An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment. | Hyunjin Kim, Jongchul Shin, Sungho Kang |
| 1999 | The MARCO/DARPA Gigascale Silicon Research Center. | Kurt Keutzer, A. Richard Newton |
| 1999 | FlexRAM: Toward an Advanced Intelligent Memory System. | Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Josep Torrellas, Pratap Pattnaik |
| 1999 | Hardware/Software Partitioning of Multirate System Using Static Scheduling Theory. | Romain Kamdem, Alain Fonkoua, Andre Zenatti |
| 1999 | Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor. | Nathan Kalyanasundharam, Nital Patwa |
| 1999 | Synthesis of Arrays and Records. | Pradip K. Jha, Steven Barnfield, John B. Weaver, Rudra Mukherjee, Reinaldo A. Bergamaschi |
| 1999 | A DSP with Caches-A Study of the GSM-EFR Codec on the TI C6211. | Tor E. Jeremiassen |
| 1999 | Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. | Abhijit Jas, Nur A. Touba |
| 1999 | Automatic Error Correction of Tri-State Circuits. | Dirk W. Hoffmann, Thomas Kropf |
| 1999 | TriMedia CPU64 Design Space Exploration. | Gerben J. Hekstra, G. D. La Hei, Peter Bingley, Frans Sijstermans |
| 1999 | Improving Microcontroller Power Consumption through a Segmented Gray Code Program Counter. | Rolf Hakenes, Yiannos Manoli |
| 1999 | Formal Verification of Synthesized Analog Designs. | Abhijit Ghosh, Ranga Vemuri |
| 1999 | Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. | Avinash K. Gautam, V. Visvanathan, S. K. Nandy |
| 1999 | A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. | Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash Chandar G. |
| 1999 | A Methodology for Rapid Prototyping of Analog Systems. | Sree Ganesan, Ranga Vemuri |
| 1999 | A Unified Method for Iterative Computation of Modular Multiplication and Reduction Operations. | William L. Freking, Keshab K. Parhi |
| 1999 | Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study. | William Fornaciari, Donatella Sciuto, Cristina Silvano |
| 1999 | The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency. | Brian R. Fisk, R. Iris Bahar |
| 1999 | System Design: Traditional Concepts and New Paradigms. | Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli |
| 1999 | TriMedia CPU64 Architecture. | Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel |
| 1999 | Multiple Paths Sensitization of Digital Oscillation Built-In Self Test. | Christian Dufaza |
| 1999 | Performance Driven Optimization of Network Length in Physical Placement. | Wilm E. Donath, Prabhakar Kudva, Lakshmi N. Reddy |
| 1999 | Conceptual Modeling and Simulation. | Walling R. Cyre |
| 1999 | Forty Five Years of Computer Architecture-All That's Old is New Again. | Harvey G. Cragon |
| 1999 | An Environment for Exploring Low Power Memory Configurations in System Level Design. | Sari L. Coumeri, Donald E. Thomas |