| 1998 | Accuracy sensitive word-length selection for algorithm optimization. | Suhrid A. Wadekar, Alice C. Parker |
| 1998 | Clock-skew constrained placement for row based designs. | Natesan Venkateswaran, Dinesh Bhatia |
| 1998 | A simple adaptive wormhole routing algorithm for MIMD systems. | Raju D. Venkataramana, N. Ranganathan |
| 1998 | Incorporating timing constraints in the efficient memory model for symbolic ternary simulation. | Miroslav N. Velev, Randal E. Bryant |
| 1998 | Current-based testing for analog and mixed-signal circuits. | Jaime Velasco-Medina, Michael Nicolaidis |
| 1998 | Evaluating the performance of active cache management schemes. | Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson |
| 1998 | A fine-grain, current mode scheme for VLSI proximity search engine. | Seiji Takeuchi, Takayasu Sakurai |
| 1998 | An approach to verify a large scale system-on-a-chip using symbolic model checking. | Koichiro Takayama, Taizo Satoh, Tsuneo Nakata, Fumiyasu Hirose |
| 1998 | A 690 ps read-access latency register file for a GHz integer microprocessor. | Osamu Takahashi, Joel Silberman, Sang H. Dhong, H. Peter Hofstee, Naoaki Aoki |
| 1998 | Learning as applied to stochastic optimization for standard cell placement. | Lixin Su, Wray L. Buntine, A. Richard Newton, Bradley S. Peters |
| 1998 | Comparative analysis of latches and flip-flops for high-performance systems. | Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa |
| 1998 | Timing verification of the 21264: A 600 MHz full-custom microprocessor. | Emily J. Shriver, Dale H. Hall, Nevine Nassif, Nadir E. Rahman, Nick L. Rethman, Gill Watt, Jim A. Farrell |
| 1998 | A minimized hardware architecture of fast Phong shader using Taylor series approximation in 3D graphics. | Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim |
| 1998 | How many logic levels does floating-point addition require? | Peter-Michael Seidel, Guy Even |
| 1998 | The ARM9 family-high performance microprocessors for embedded applications. | Simon Segars |
| 1998 | To model check or not to model check. | Nina Saxena, Jason Baumgartner, Avijit Saha, Jacob A. Abraham |
| 1998 | Efficient exact and heuristic minimization of hazard-free logic. | J. W. J. M. Rutten, Michel R. C. M. Berkelaar |
| 1998 | Software power estimation and optimization for high performance, 32-bit embedded processors. | Jeffry T. Russell, Margarida F. Jacome |
| 1998 | A reduction scheme to optimize the Wallace multiplier. | Moises E. Robinson, Earl E. Swartzlander Jr. |
| 1998 | Methods for calculating coupling noise in early design: a comparative analysis. | Khalid Rahmat, Jos Neves, Jin-Fuw Lee |
| 1998 | A fractal compaction algorithm for efficient power estimation. | Radj Radjassamy, Jo Dale Carothers |
| 1998 | Partitioning in time: a paradigm for reconfigurable computing. | Karthikeya M. Gajjala Purna, Dinesh Bhatia |
| 1998 | Design issues in mixed static-domino circuit implementations. | Ruchir Puri |
| 1998 | Design methodology for a 1.0 GHz microprocessor. | Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo |
| 1998 | Improved built-in test pattern generators based on comparison units for synchronous sequential circuits. | Irith Pomeranz, Sudhakar M. Reddy |