| 1998 | The system design of a Windows CE ARM based micro-controller. | Keith S. P. Clarke, Danny Kershaw |
| 1998 | Practical use of transition mode delay to solve the problems of floating mode delay under highly correlated input streams. | Hoon Choi, Seung Ho Hwang |
| 1998 | Pipelined computation of LNS addition/subtraction with very small lookup tables. | Chichyang Chen, Chih-Huan Yang |
| 1998 | Efficient BIST TPG design and test set compaction for delay testing via input reduction. | Chih-Ang Chen, Sandeep K. Gupta |
| 1998 | Practical design and performance evaluation of completion detection circuits. | Fu-Chiung Cheng |
| 1998 | Area-oriented synthesis for pass-transistor logic. | Rajat Chaudhry, Tai-Hung Liu, Adnan Aziz, Jeffrey L. Burns |
| 1998 | High-performance digit-serial complex-number multiplier-accumulator. | Yun-Nan Chang, Keshab K. Parhi |
| 1998 | The effects of explicitly parallel mechanisms on the multi-ALU processor cluster pipeline. | Andrew Chang, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Whay Sing Lee |
| 1998 | Leading-one prediction scheme for latency improvement in single datapath floating-point adders. | Javier D. Bruguera, Toms Lang |
| 1998 | Optimal design of synchronous circuits using software pipelining techniques. | Franois R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Imed Eddine Bennour |
| 1998 | An effective datapath design methodology for high-frequency design. | Carina Ben-Zvi, Patrick McGuinness, Franklin Lassandro |
| 1998 | Hierarchical pipelining for behaviors, loops, and operations. | Smita Bakshi, Daniel D. Gajski |
| 1998 | System-level performance estimation strategy for sw and hw. | Alberto Allara, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto |
| 1998 | A low-power logic optimization methodology based on a fast power-driven mapping. | Sumit Roy, Harm Arts, Prithviraj Banerjee |
| 1997 | Critical Voltage Transition Logic: An Ultrafast CMOS Logic Family. | Zhang Zhu, Bradley S. Carlson |
| 1997 | Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation. | Hai Zhou, D. F. Wong |
| 1997 | Multi-Column Implementations for Cache Associativity. | Chenxi Zhang, Xiaodong Zhang, Yong Yan |
| 1997 | Architectural Adaptation for Application-Specific Locality Optimization. | Xingbin Zhang, Ali Dasdan, Martin Schulz, Rajesh K. Gupta, Andrew A. Chien |
| 1997 | On the Construction of Universal Series-Parallel Functions for Logic Module Design. | Fung Yu Young, D. F. Wong |
| 1997 | A High-Frequency Custom CMOS S/390 Microprocessor. | Charles F. Webb, John S. Liptay |
| 1997 | High-Performance CMOS Circuit Techniques for the G-4 S/390 Microprocessor. | James D. Warnock, Leon J. Sigal, Brian W. Curran, Yuen H. Chan |
| 1997 | Development of Hierarchical Testability Design Methodologies for Analog/Mixed-Signal Integrated Circuits. | Cheng-Ping Wang, Chin-Long Wey |
| 1997 | Estimation of Maximum Power for Sequential Circuits Considering Spurious Transitions. | Chuan-Yu Wang, Kaushik Roy |
| 1997 | Post Layout Speed-up by Event Elimination. | Hirendu Vaishnav, Chi-Keung Lee, Massoud Pedram |
| 1997 | A 400MHz, 144Kb CMOS ROM Macro for an IBM S/390-Class Microprocessor. | Arthur Tuminaro |